Architecture for a flash erase EEPROM memory

Details Architecture for a flash erase EEPROM memory Architecture for a flash erase EEPROM memory

1988-11-23

1991-03-12

Moffitt, James W.

Static information storage and retrieval

Floating gate

Particular biasing

365203, 357 235, G11C 700, G11C 1140

Patent

active

049998129

ABSTRACT:
An EEPROM device provides increased speed and less susceptibility to soft writes during reading and programming operations. A unique circuit design and operating method obviates the need for applying a high programming or erase voltage in the path between the memory array and sense amplifier. Such high programming and erase voltages are applied, as needed, directly to the memory array, thereby allowing all transistors which carry signals from the memory array to the sense amplifier to be fabricated as low voltage devices, thereby increasing their speed of operation and thus the speed of operation of the memory device as a whole. By applying the relatively high programming and erase voltages to the source of the memory transistors, and reading from the drain of the memory transistors, the source and drain as well as associated circuitry are fabricated to optimize their intended functions.

REFERENCES:
patent: 4462090 (1984-07-01), Iizuka
patent: 4852062 (1989-07-01), Baker et al.

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