Applying different body bias to different substrate portions...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185270, C365S185180

Reexamination Certificate

active

08000146

ABSTRACT:
Body bias can be applied to optimize performance in a non-volatile storage system. Body bias can be set in an adaptive manner to reduce an error count of an error correcting and/or detecting code when reading data from non-volatile storage elements. Also, a body bias level can be increased or decreased as a number of programming cycles increases. Also, body bias levels can be set and applied separately for a chip, plane, block and/or page. A body bias can be applied to a first set of NAND strings for which operations are being performed by controlling a first voltage provided to a source side of the first set of NAND strings and a second voltage provided to a p-well. A source side of a second set of NAND strings for which operations are not being performed is floated or receives a fixed voltage.

REFERENCES:
patent: 5386422 (1995-01-01), Endoh
patent: 5467306 (1995-11-01), Kaya
patent: 5522580 (1996-06-01), Varner, Jr.
patent: 5570315 (1996-10-01), Tanaka
patent: 5774397 (1998-06-01), Endoh
patent: 6046935 (2000-04-01), Takeuchi
patent: 6175522 (2001-01-01), Fang
patent: 6218895 (2001-04-01), De
patent: 6222762 (2001-04-01), Guterman
patent: 6272666 (2001-08-01), Borkar
patent: 6301155 (2001-10-01), Fujiwara
patent: 6363016 (2002-03-01), Lin
patent: 6366499 (2002-04-01), Wang
patent: 6456528 (2002-09-01), Chen
patent: 6484265 (2002-11-01), Borkar
patent: 6522580 (2003-02-01), Chen
patent: 6560152 (2003-05-01), Cernea
patent: 6577530 (2003-06-01), Muranaka
patent: 6734490 (2004-05-01), Esseni
patent: 6751125 (2004-06-01), Prinz
patent: 6771536 (2004-08-01), Li
patent: 6801454 (2004-10-01), Wang
patent: 6839281 (2005-01-01), Chen
patent: 6859397 (2005-02-01), Lutze
patent: 6870213 (2005-03-01), Cai
patent: 6900650 (2005-05-01), Sheng
patent: 6917237 (2005-07-01), Tschanz
patent: 6957163 (2005-10-01), Ando
patent: 7009881 (2006-03-01), Noguchi
patent: 7046568 (2006-05-01), Cernea
patent: 7057958 (2006-06-01), So
patent: 7116588 (2006-10-01), Joo
patent: 7170785 (2007-01-01), Yeh
patent: 7196928 (2007-03-01), Chen
patent: 7242622 (2007-07-01), Hsu et al.
patent: 7244976 (2007-07-01), Cai
patent: 7292476 (2007-11-01), Goda
patent: 7345913 (2008-03-01), Isobe
patent: 7394708 (2008-07-01), Vadi
patent: 7468919 (2008-12-01), Sekar
patent: 7468920 (2008-12-01), Sekar
patent: 7525843 (2009-04-01), Sekar et al.
patent: 2002/0140496 (2002-10-01), Keshavarzi
patent: 2004/0057287 (2004-03-01), Cernea
patent: 2004/0109357 (2004-06-01), Cernea
patent: 2004/0255090 (2004-12-01), Guterman
patent: 2005/0024939 (2005-02-01), Chen
patent: 2005/0052219 (2005-03-01), Butler
patent: 2005/0111260 (2005-05-01), Nazarian
patent: 2005/0144516 (2005-06-01), Gonzalez et al.
patent: 2005/0192773 (2005-09-01), Sheng
patent: 2006/0126390 (2006-06-01), Gorobets
patent: 2006/0133172 (2006-06-01), Schnabel
patent: 2006/0140007 (2006-06-01), Cernea
patent: 2006/0158947 (2006-07-01), Chan
patent: 2006/0226889 (2006-10-01), Gupta
patent: 2006/0227613 (2006-10-01), Joo
patent: 2007/0008779 (2007-01-01), Isobe
patent: 2007/0247907 (2007-10-01), Chang et al.
patent: 2008/0084764 (2008-04-01), Pikhay et al.
patent: 2008/0158970 (2008-07-01), Sekar
patent: 2008/0159007 (2008-07-01), Sekar
patent: 2009/0097319 (2009-04-01), Sekar et al.
patent: 411045986 (1999-02-01), None
patent: 411250681 (1999-09-01), None
D.H. Kang et al., Novel Heat Dissipating Cell Scheme For Improving A Reset Distribution in a 512M Phase-Change Random Access Memory (PRAM), 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 96-97, Jun. 14-16, 2007.
N. Shibata et al., A 70nm 16Gb 16-level-cell NAND Flash Memory, 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 190-191, Jun. 14-16, 2007.
H. Tanaka et al., Bit Cost Scalable Technology With Punch And Plug Process For Ultra High Density Flash Memory, 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 14-15, Jun. 14-16, 2007.
Y. Zhang et al., An Integrated Phase Change Memory Cell With Ge Nanowire Diode for Cross-Point Memory, 2007 Symp. on VLSI Circuits Digest of Technical Papers, pp. 98-99, Jun. 14-16, 2007.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Applying different body bias to different substrate portions... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Applying different body bias to different substrate portions..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Applying different body bias to different substrate portions... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2694058

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.