Architecture for a flash-EEPROM simultaneously readable in...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185110, C365S185120

Reexamination Certificate

active

06891755

ABSTRACT:
A memory device includes an array of memory cells organized into a plurality of sectors, and local wordlines and local bitlines are connected to the memory cells in each respective sector. Main read wordlines and main program wordlines are connected to the local wordlines in each sector. A main read row decoder is connected to the main read wordlines, and a main program row decoder connected to the main program wordlines. Main read bitlines and main program bitlines are connected to the local bitlines in each sector. A main read column decoder is connected to the main read bitlines, and a main program column decoder is connected to the main program wordlines. A read address bus is connected to the main read row decoder and to the main read column decoder for providing an address thereto. A program address bus is connected to the main read column decoder and to the main program row decoder for providing an address thereto.

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patent: 6456530 (2002-09-01), Micheloni et al.
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