Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2001-08-13
2003-02-11
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185180, C365S185200, C365S185220, C365S185290
Reexamination Certificate
active
06519180
ABSTRACT:
FIELD OF THE INVENTION
This invention relates in general to semiconductor memories and, in particular, to the design and operation of multilevel nonvolatile semiconductor memories.
BACKGROUND OF THE INVENTION
As the information technology progresses, the demand for high density giga bit and tera bit memory integrated circuits is insatiable in emerging applications such as data storage for photo quality digital film in multi-mega pixel digital camera, CD quality audio storage in audio silicon recorder, portable data storage for instrumentation and portable personal computers, and voice, data, and video storage for wireless and wired phones and other personal communicating assistants.
The nonvolatile memory technology such as ROM (Read Only Memory), EEPROM (Electrical Erasable Programmable Read Only Memory), or FLASH is often a technology of choice for these application due to its nonvolatile nature, meaning it still retains the data even if the power supplied to it is removed. This is in contrast with the volatile memory technology such as DRAM (Dynamic Random Access Memory), which loses data if the power supplied to it is removed. This nonvolatile feature is very useful in.saving the power from portable supplies such as batteries. Until battery technology advances drastically to ensure typical electronic systems to function for a typical operating lifetime, e.g., 10 years, the nonvolatile echnology will fill the needs for most portable applications.
The FLASH technology, due to its smallest cell size, is the highest density nonvolatile memory system currently available. The advance of the memory density is made possible by rapidly advancing the process technology into the realm of nano meter scale and possibly into the atomic scale and electron scale into the next century. At the present sub-micro meter scale, the other method that makes the super high-density memory system possible is through the exploitation of the analog nature of a storage element.
The analog nature of a flash or nonvolatile storage element provides, by theory, an enormous capability to store information. For example, if one electron could represent one bit of information then, for one typical conventional digital memory cell, the amount of information is equal to the number of electrons stored, or approximately a few hundred thousands. Advances in device physics exploring the quantum mechanical nature of the electronic structure will multiply the analog information manifested in the quantum information of a single electron even further.
The storage information in a storage element is hereby defined as a discrete number of storage levels for binary digital signal processing with the number of storage levels equal to 2
N
with N equal to the number of digital binary bits. The optimum practical number of discrete levels stored in a nonvolatile storage element depends on the innovative circuit design method and apparatus, the intrinsic and extrinsic behavior of the storage element, all within constraints of a definite performance target such as product speed and operating lifetime within a certain cost penalty.
At the current state of the art, all the multilevel systems are only suitable for medium density, i.e. less than a few tens of mega bits, and only suitable for a small number of storage levels per cell, i.e., less than four levels or two digital bits.
As can be seen, memories having high storage capacity and fast operating speed are highly desirable.
SUMMARY OF THE INVENTION
This invention describes the design method and apparatus for a super high density nonvolatile memory system capable of giga bits as applied to the array architecture, reference system, and decoding schemes to realize the optimum possible number of storage levels within specified performance constraints. Method and apparatus for multilevel program and sensing algorithm and system applied to flash memory is also described in this invention. Details of the invention and alternative embodiments will be made apparent by the following descriptions.
The invention provides array architectures and operating methods suitable for a super high density, in the giga bits, for multilevel nonvolatile “green” memory integrated circuit system. “Green” refers to a system working in an efficient and low power consumption manner. The invention solves the issues associated with super high density multilevel memory system, such as, precisionvoltage control in the array, severe capacitive loading from MOS transistor gates and parasitics, high leakage current due to memory cells and from cells to cells, excessive power consumption due to large number of gates and parasitics, and excessive memory cell disturbs due to large memory density.
An aspect of the invention provides an Inhibit and Select Segmentation Scheme that makes use of a truly-floating-bitline scheme to greatly reduce the capacitance from junctions and parasitic interconnects to a small value.
The invention also provides a Multilevel Memory Decoding scheme which is capable of greater than 10-bit multilevel operation. The Multilevel Memory Decoding Scheme includes the Power Supply Decoded Decoding Scheme, the Feedthrough-to-Memory Decoding Scheme, and the Feedthrough-to-Driver Decoding Scheme. The Multilevel Memory Decoding scheme also includes a “winner-take-all” Kelvin Decoding Scheme, which provides precise bias levels for the memory at a minimum cost. The invention also provides a constant-total-current-program scheme. The invention also provides fast-slow and 2-step ramp rate control programming. The invention also presents reference system method and apparatus, which includes the Positional Linear Reference System, Positional Geometric Reference System, and the Geometric Compensation Reference System. The invention also describes apparatus and method of multilevel programming, reading, and margining.
Method and apparatus described herein are applicable to digital multilevel as well as analog multilevel system.
REFERENCES:
patent: 5218569 (1993-06-01), Banks
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5539690 (1996-07-01), Talreja
patent: 5596526 (1997-01-01), Assar et al.
Khan Sakhawat M.
Korsh George J.
Tran Hieu Van
Dinh Son T.
Gray Cary Ware & Freidenrich LLP
Silicon Storage Technology, Inc.
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