Bias structure of a flash memory
Biasing circuit and method to achieve compaction and self-limiti
Biasing circuit for EEPROM memories with shared latches
Biasing circuit for UPROM cells with low voltage supply
Biasing method and structure for reducing band-to-band and/or av
Biasing method and structure for reducing band-to-band...
Biasing non-volatile storage based on selected word line
Biasing scheme for reducing stress and improving reliability in
Biasing scheme to reduce stress on non-selected cells during rea
Biasing stage for biasing the drain terminal of a...
Bit and block erasing of an electrically erasable and programmab
Bit by bit APDE verify for flash memory applications
Bit latch scheme for parallel program verify in floating gate me
Bit line control circuit for a memory array using 2-bit non-vola
Bit line control circuit for semiconductor memory device
Bit line control circuit for semiconductor memory device
Bit line decoding scheme and circuit for dual bit memory array
Bit line discharge method for reading a multiple bits-per-cell f
Bit line pre-settlement circuit and method for flash memory...
Bit line precharge circuit