Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2005-11-16
2008-03-11
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S185210, C365S203000, C365S210130, C365S207000
Reexamination Certificate
active
07342832
ABSTRACT:
A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.
REFERENCES:
patent: 4816706 (1989-03-01), Dhong et al.
patent: 5007023 (1991-04-01), Kim et al.
patent: 5305273 (1994-04-01), Jinbo
patent: 5339274 (1994-08-01), Dhong et al.
patent: 5361229 (1994-11-01), Chiang et al.
patent: 5396467 (1995-03-01), Liu et al.
patent: 5434822 (1995-07-01), Deleganes et al.
patent: 5528543 (1996-06-01), Stiegler
patent: 5530671 (1996-06-01), Hashimoto
patent: 5559737 (1996-09-01), Tanaka et al.
patent: 5563831 (1996-10-01), Ting
patent: 5594691 (1997-01-01), Bashir
patent: 5781469 (1998-07-01), Pathak et al.
patent: 5848015 (1998-12-01), Seno
patent: 5864503 (1999-01-01), Pascucci
patent: 5875139 (1999-02-01), Semi
patent: 5883845 (1999-03-01), Khang
patent: 5963494 (1999-10-01), Khang
patent: 6021072 (2000-02-01), Takeda et al.
patent: 6023435 (2000-02-01), Narayana et al.
patent: 6098145 (2000-08-01), Huang
patent: 6240020 (2001-05-01), Yang et al.
patent: 6426914 (2002-07-01), Dennard et al.
patent: 6490212 (2002-12-01), Nguyen et al.
patent: 6504775 (2003-01-01), Ma et al.
patent: 6567327 (2003-05-01), Tsuchi
patent: 6608788 (2003-08-01), Ma et al.
patent: 6643804 (2003-11-01), Aipperspach et al.
patent: 6667921 (2003-12-01), Park
patent: 6717856 (2004-04-01), Srinivasan et al.
patent: 6856563 (2005-02-01), Kim et al.
patent: 2003/0016580 (2003-01-01), Ma et al.
patent: 2003/0072205 (2003-04-01), Ma et al.
patent: 2003/0123311 (2003-07-01), Park
patent: 2004/0076070 (2004-04-01), Kim et al.
patent: 2004/0151044 (2004-08-01), Kant et al.
patent: 2005/0105354 (2005-05-01), Madan
Lee Poongyeub
Liu MingChi Mitch
Actel Corporation
Hur J. H.
Sierra Patent Group Ltd.
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