Bit and block erasing of an electrically erasable and programmab

Details Bit and block erasing of an electrically erasable and programmab Bit and block erasing of an electrically erasable and programmab

1989-06-30

1991-09-10

Gossage, Glenn

Static information storage and retrieval

Floating gate

Particular biasing

365218, 3652385, G11C 1604

Patent

active

050479814

ABSTRACT:
A method for either block- or bit-erasing is described for an array of EEPROM cells, each having transistor channel regions with subchannels thereof respectively controlled by a floating gate conductor and a control gate. Erasing occurs through a Fowler-Nordheim tunnel window (34) between a source bit line (24) and a floating gate conductor (42) of a selected cell. For one or more selected cells, first and second erasing voltages are selected such that the selected source bit line (24) is more positive than the selected word line (48) by a voltage sufficient to cause excess electrons on the floating gate conductor (42) to be drawn through the tunnel window (34) to the source region (24). The nonselected word lines (48) have a nonerasing voltage impressed thereon that is sufficiently close to that of selected source regions that no erase disturb will occur in nonselected cells.

REFERENCES:
patent: 4064494 (1977-12-01), Dickson et al.
patent: 4112509 (1978-09-01), Wall
patent: 4130890 (1978-12-01), Adam
patent: 4377857 (1983-03-01), Tickle
patent: 4451905 (1984-05-01), Moyer
patent: 4511996 (1985-04-01), Jacobs
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 4924437 (1990-05-01), Paterson et al.
patent: 4949309 (1990-08-01), Rao

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