Biasing scheme to reduce stress on non-selected cells during rea

Details Biasing scheme to reduce stress on non-selected cells during rea Biasing scheme to reduce stress on non-selected cells during rea

1999-10-29

2000-11-14

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518533, G11C 1604

Patent

active

061479071

ABSTRACT:
A method of reading a flash memory (EEPROM) device by applying zero volts to all bitlines and source terminals in the flash memory device. A negative voltage (V.sub.D) is applied to all the substrate and all wordlines in the flash memory device. The negative voltage (-V.sub.D) is applied to the bitline to which the drain of the cell being read is attached and applying a positive voltage (V.sub.G) minus the voltage V.sub.D to the wordline to which the gate of the cell being read is attached.

REFERENCES:
patent: 5905675 (1999-05-01), Madurawe et al.

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