Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-11-27
2002-02-26
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185230
Reexamination Certificate
active
06351414
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a flash memory, and more particularly to, a bias structure of a flash memory capable of reducing a chip size.
BACKGROUND OF THE INVENTION
Generally, a flash memory is set to have the highest voltage when reading the power supply supplied to a word line W/L, upon reading of the threshold voltage of the program cell.
FIG. 1
is a block diagram for explaining a bias structure in a conventional flash memory.
The conventional flash memory bias structure is consisted of a word line pump
11
for pumping the power supply Vcc, a first voltage regulating unit
12
for regulating the output voltage of the word line pump
11
, a X decoder
30
for supplying the output from the first voltage regulating unit
12
to a word line W/L in a flash cell M
1
, a drain pump
21
for pumping the drain of the flash cell M
1
and a second voltage regulating unit
22
for regulating the output voltage from the drain pump
21
.
The above word line pump
11
pumps the supply power Vcc in a program mode (program signal PGM is at High signal), whereas it outputs the supply power Vcc intact in a read mode (program signal PGM is at Low signal). The first voltage regulating unit
12
regulates the voltage pumped by the word line pump
11
to VPPX during a program mode, whereas it outputs the supply power Vcc outputted from the word line pump
11
to the X decoder
30
, without regulating the voltage during a read mode.
The drain pump
21
pumps the supply power Vcc using an enable signal EN. The second regulating unit
22
regulates the voltage pumped by the drain pump
21
to VPPD, using the enable signal EN, and then supplies it to the drain D of the cell M
1
.
In order to down-regulate the threshold voltage of the program cell, the conventional flash memory bias structure regulates the supply power to a specific level upon reading and then applies the regulated voltage to a selected word line W/L, so that the threshold voltage of the program cell can be down-regulated. However, the conventional bias structure includes a drain pump in order to supply the drain voltage to the drain of the cell. Therefore, the conventional bias structure has drawbacks that the chip size is increased and the consumption power is great.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a bias structure of a flash memory capable of consumption power and chip size.
In order to accomplish the above object, a bias structure of a flash memory according to the present invention is characterized in that it comprises a word line pump for pumping a power supply, in a program mode, and outputting the power supply, in a read mode, a first voltage regulating unit for regulating the output voltage of the word line pump at a given voltage, in the program mode, and regulating the power supply at a specific level, in the read mode, thus outputting it, and a X decoder for supplying the output voltage from the first voltage regulating unit to a word line in a cell.
REFERENCES:
patent: 5519656 (1996-05-01), Maccarrone et al.
patent: 5812456 (1998-09-01), Hull et al.
patent: 5815445 (1998-09-01), Hull et al.
patent: 5835420 (1998-11-01), Lee et al.
patent: 5889701 (1999-03-01), Kang et al.
patent: 6002630 (1999-12-01), Chuang et al.
patent: 6122205 (2000-09-01), Yach
patent: 6128242 (2000-10-01), Bamba et al.
patent: 6172917 (2001-01-01), Kataoka et al.
Lebentritt Michael S.
Pennie & Edmonds LLP
Phung Anh
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