Biasing circuit for EEPROM memories with shared latches

Details Biasing circuit for EEPROM memories with shared latches Biasing circuit for EEPROM memories with shared latches

2007-10-26

2010-06-22

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185110

Reexamination Certificate

active

07742342

ABSTRACT:
An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.

REFERENCES:
patent: 6639838 (2003-10-01), Fournel et al.

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