Biasing circuit and method to achieve compaction and self-limiti

Details Biasing circuit and method to achieve compaction and self-limiti Biasing circuit and method to achieve compaction and self-limiti

1995-02-13

1996-06-11

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

3651852, 36518527, G11C 1602

Patent

active

055263151

ABSTRACT:
The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11) to a source voltage (Vs) having a higher potential than the control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

REFERENCES:
patent: 4797856 (1989-01-01), Lee et al.
patent: 5220528 (1993-06-01), Mielke
patent: 5220533 (1993-06-01), Turner
patent: 5331592 (1994-07-01), Yamagata
patent: 5357463 (1994-10-01), Kinney
patent: 5357466 (1994-10-01), Hong
patent: 5357476 (1994-10-01), Kuo et al.
patent: 5361235 (1994-11-01), Kodama
patent: 5428578 (1995-06-01), Kaya et al.

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