Biasing stage for biasing the drain terminal of a...

Details Biasing stage for biasing the drain terminal of a... Biasing stage for biasing the drain terminal of a...

2000-06-02

2001-11-20

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185210

Reexamination Certificate

active

06320790

ABSTRACT:

TECHNICAL FIELD
The present invention regards a biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase.
BACKGROUND OF THE INVENTION
As is known, in a floating gate nonvolatile memory cell storage of a logic state is carried out by programming the threshold voltage of the cell itself through the definition of the quantity of electrical charge stored in the floating gate region.
According to the information stored, memory cells may be distinguished into erased memory cells (logic state stored “1”), in which no electrical charge is stored in the floating gate region, and written or programmed memory cells (logic state stored “0”), in which an electrical charge is stored in the floating gate region that is sufficient to determine a sensible increase in the threshold voltage of the memory cell itself.
It is also known that reading of a memory cell consists in converting the current absorbed by the memory cell, at a given gate-source voltage, into a voltage which is then translated to a CMOS level at output from a special comparator circuit.
In particular, to carry out reading of a memory cell, a read voltage is supplied to the gate terminal of the cell which has a value comprised between the threshold voltage of an erased memory cell and that of a written memory cell, in such a way that, if the memory cell is written, the read voltage is lower than the threshold voltage, and hence no current flows in the cell, whereas, if the memory cell is erased, the read voltage is higher than the threshold voltage, and hence current flows in the cell.
Reading of a memory cell is carried out using a read circuit known as “sense amplifier”, which, in addition to recognizing the logic state stored in the memory cell, also provides for the correct biasing of the drain terminal of the memory cell. During the read phase, the drain terminal of a memory cell is in fact biased with a voltage of approximately 1 V, which is obtained as a compromise between a maximum value that is not to be exceeded in order to avoid the so-called “soft writing” phenomenon, i.e., spurious writing of the memory cell during reading of the same, and a minimum value, below which the intensity of the current flowing in the memory cell is excessively small and would require, on the one hand, the use of an extremely precise sense amplifier, and thus one more complex and costly, in order to carry out correct reading of the logic state stored in the cell, and further would usually lead to a degradation in performance in terms of reading speed.
In order to provide an example,
FIG. 1
shows the output characteristics I
DS
=f(V
GS
) of a memory cell, which link the gate-source voltage V
GS
to the drain-source current I
DS
of a memory cell, for values of the voltage VD of the drain terminal of the memory cell of 1 V, 0.8 V and 0.5 V, and in which it is evident that as the voltage V
D
of the drain terminal of the memory cell decreases, there is a corresponding decrease in the drain-source current I
DS
flowing in the memory cell, given the same gate-source voltage V
GS
.
FIG. 2
shows one of the classic circuit diagrams of a sense amplifier, in which, for reasons of simplicity, the column decoding, which enables a single column of the memory array to be selected at a time, has been omitted.
According to what is illustrated in the above-mentioned figure, the sense amplifier, indicated as a whole by 1, comprises a supply line
2
set at a supply voltage V
CC
(for example, between 2.5 and 3.8 V), a ground line
3
set at the ground voltage V
GND
(for example, 0 V), an array branch
4
connected, via an array bit line
5
, to an array cell
6
, the content of which is to be read, and a reference branch
8
connected, via a reference bit line
10
, to a reference cell
11
, the content of which is known.
In particular, the array cell
6
and the reference cell
11
have gate terminals receiving the same read signal V
READ
, drain terminals connected to the array bit line
5
and, respectively, to the reference bit line
10
, and source terminals connected to the ground line
3
.
The array branch
4
comprises an array biasing stage
12
for biasing the drain terminal of the array cell
6
, comprising a fedback cascode structure formed of an NMOS transistor
14
and a NOR logic gate
20
. In particular, the NMOS transistor
14
has a source terminal connected to the array bit line
5
, a drain terminal connected, via a diode-connected PMOS transistor
16
, to the supply line
2
, and a gate terminal connected to an output terminal of the NOR logic gate
20
, which in turn has a first input terminal receiving a control signal ENS and a second terminal connected to the source terminal of the NMOS transistor
14
.
The control signal ENS is a logic signal, the low logic level of which enables operation of the sense amplifier
1
, whilst its high logic level disables operation of the sense amplifier
1
.
The reference branch
8
comprises a reference biasing stage
21
for biasing the drain terminal of the reference cell
11
, comprising an NMOS transistor
22
having a source terminal connected to the reference bit line
10
, a drain terminal connected, via a PMOS transistor
24
, to the supply line
2
, and a gate terminal connected to an output terminal of a NOR logic gate
26
, which has a first input terminal receiving the control signal ENS and a second terminal connected to the source terminal of the NMOS transistor
22
.
The PMOS transistors
16
,
24
form a current mirror
28
carrying out the aforementioned current-to-voltage conversion, and in particular have gate terminals connected together and to the drain terminal of the PMOS transistor
16
, source terminals connected to the supply line
2
, and drain terminals connected to the drain terminals of the NMOS transistor
14
and, respectively, of the NMOS transistor
22
and defining an array node
30
and a reference node
32
, respectively.
Finally, the sense amplifier
1
comprises a comparator
34
having a non-inverting input terminal connected to the array node
30
, an inverting input terminal connected to the reference node
32
, and an output terminal on which a logic signal is supplied that is indicative of the logic state stored in the array cell
6
.
Connected to the array bit line
5
are moreover a number of array cells
6
arranged on the same array column, the capacitances of which are represented schematically in
FIG. 1
by a equivalent array capacitor
36
.
As shown in greater detail in
FIG. 3
, each NOR gate
20
,
26
comprises an inverter
40
formed of a pull down NMOS transistor
42
and a pull up PMOS transistor
44
having gate terminals connected together and to the source terminals of the NMOS transistors
14
and
22
, respectively, and drain terminals connected together and to the gate terminals of the NMOS transistors
14
and
22
, respectively. The NMOS transistor
42
further has a source terminal connected to ground, whilst the PMOS transistor
44
has a source terminal connected to a drain terminal of a PMOS transistor
46
having a source terminal connected to the supply line
2
and a gate terminal receiving the control signal ENS.
Finally, each NOR logic gate
20
,
26
comprises an NMOS transistor
48
having a gate terminal receiving the control signal ENS, a source terminal connected to ground, and the drain terminal connected to the drain terminals of the NMOS transistor
42
and the PMOS transistor
44
.
The NOR logic gate
20
drives in feedback the NMOS transistor
14
, which operates in cascode configuration, performing the following three different functions.
The first function performed by the NMOS transistor
14
is that of decoupling the array node
30
from the array bit line
5
, and this has positive effects on the reading speed. In fact, the capacitance of the equivalent array capacitor
36
depends upon the parameters of the technological process and upon the type of architecture of the memory array, and, in any case, it is of several pF as compared to the tens of fF of the

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