Biasing method and structure for reducing band-to-band and/or av

Details Biasing method and structure for reducing band-to-band and/or av Biasing method and structure for reducing band-to-band and/or av

1997-12-18

1999-12-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518517, G11C 1134

Patent

active

060058080

ABSTRACT:
A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

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Haddad, Sameer, et al., "An Investigation of Erase-Mode Dependent Hole Trapping in Flash EEPROM Memory Cell", IEEE Electron Device Letters, vol. 11, No. 11, Nov., 1990, pp. 514-516.
Chang, Chi, et al., "Drain-Avalanche and Hole-Trapping Induced Gate Leakage in Thin-Oxide MOS Devices", IEEE Electron Device Letters, vol. 9, No., 11, Nov. 1988, pp. 588-590.

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