Bit line decoding scheme and circuit for dual bit memory array

Details Bit line decoding scheme and circuit for dual bit memory array Bit line decoding scheme and circuit for dual bit memory array

2002-07-08

2003-10-07

Lam, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185030, C365S185110, C365S230040

Reexamination Certificate

active

06631089

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention applies to semiconductor memories and in particular to a dual bit twin MONOS memory array.
2. Description of Related Art
Both Flash and MONOS EEPROM are comprised of an array of cells that can be independently programmed and read. Select transistors can be added to the array to cut the capacitance on lines, and can be used to enable cells to be erased. Metal Oxide Semiconductor (MOS) field effect transistors are the individual memory units of both types of EEPROMS. The Flash MOS transistor includes a source, drain, and floating gate with a control gate connected to a Word Line (WL). Various voltages are applied to the word line to program the cell with a binary “1”, or “0” or to erase the cell.
In the conventional MONOS MOS transistor the programmable component under the control gate is a nitride layer ML and MR as shown in FIG.
1
. The twin MONOS memory cell, CELL[X], is comprised of a control gate CG with a left and right component, CG_L and CG_R, under which two separate sites, ML and MR, are used as storage sites in the composite nitride layer. The bit line diffusion, BL, lies under the control gate, CG, and an independent polysilicon word line, WL, lies between the control gates of adjacent cells. Various voltages applied to the control gate CG in combination with bit line BL and word line WL voltages are used to program the left and right cell components with a binary “1” or “0”.
The array scheme U.S. Pat. No. 6,011,725 (Eitan) is directed toward a polysilicon word line routed above the control gates of the cells connected to the word line WL. U.S. Pat. No. 6,248,633 (Ogura et al) is directed toward a twin MONOS cell structure having an ultra short control gate channel with ballistic electron injection into the nitride storage sites and fast low voltage programming. U.S. patent application Ser. No. 10/099,030 dated Mar. 15, 2002 is directed toward providing a method of memory cell selection and operation to obtain wide program bandwidth and EEPROM erase capability in a MONOS memory cell. U.S. patent application Ser. No. 09/810,122 dated Mar. 19, 2001 is directed toward an array architecture of nonvolatile memory and its operation methods using a metal bit diffusion array.
In
FIG. 1
is shown a cross section of part of an array of twin MONOS memory cells of prior art. Within a twin MONOS cell such as CELL[X] is a control gate CG having a left CG_L and a right CG_R control gate component. Under the left control gate component CG_L lies a left nitride storage site ML, and under the right control gate component CG_R lies a right nitride storage site MR. A bit line diffusion BL lies within the semiconductor substrate and positioned under the control gate CG and between the left and right storage sites, ML and MR. A word line WL running orthogonal to the bit line BL separates adjacent cells.
In
FIG. 2
is shown a schematic diagram of prior art of a portion of an array structure formed by the twin MONOS memory cells of FIG.
1
. The control gate lines CG[
0
], CG[
1
], CG[
2
] and CG[
3
] run in parallel with the bit lines BL[
0
], BL[
1
], BL[
2
] and BL[
3
], and orthogonal to the word lines WL[
0
] and WL[
1
]. Shown within the outline of CELL[X] are the left and right control gate components CG_L and CG_R under which are the left and right storage sites ML and MR.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a bit line decoding scheme for a twin MONOS memory array.
It is also an objective of the present invention to provide a decoder circuit capable of selecting and controlling bit lines of an array of twin MONOS memory cells to permit reading and programming the twin storage sites of each cell.
It is another objective of the present invention to provide a first decode circuit for even numbered bit lines and a second decode circuit for odd numbered bit lines.
It is still another objective of the present invention to control adjacent bit lines separately from selected bit lines.
It is yet another objective of the present invention to apply a voltage to the bit line used in reading the left and right storage sites of a selected cell and apply a separate voltage to bit lines in adjacent cells.
It is also another objective of the present invention to apply a voltage to the bit line of a selected cell during a program operation and to apply a separate voltage to the bit line to a cell adjacent to the storage site being programmed.
The present invention is essentially a multiplexer for the bit line diffusions of a twin MONOS memory array, where a twin MONOS cell comprises two side by side control gates under which are two nitride storage sites that share a bit line single diffusion. During a read operation a specific voltage is applied to the single bit line diffusion, and a separate voltage is applied to the bit line diffusions of the two adjacent cells. All other diffusions within a sub-block are unselected and floating. The voltage application on the selected bit line diffusion and the two neighboring bit line diffusions for a read operation remain the same whether the control gate being used to read is on the left or the right control gate. However, for a program operation only the bit line diffusion of the selected cell and the bit line diffusion of the neighbor cell closest to the storage site being programmed are selected. If the left storage site under the left control gate of the selected cell is to be programmed, the bit line diffusion in the cell to the left of the cell being programmed is concurrently supplied a separate voltage. If the right storage site under the right control gate of the selected cell is to be programmed, then the bit line diffusion in the cell to the right of the cell being programmed is concurrently supplied a separate voltage. Both these conditions for the program operation are met by a design of a separate MUX for even and odd bit lines. While one bit line is selected by a first MUX for a program operation, the adjacent cells are selected by a second MUX.
If there are X=number of Cells on a word line, then the word line is divided into Y blocks, where Y is the number of sense amplifiers or I/O's, and Z=X/Y where Z the number of cells per block. Depending on the parasitic capacitance, the word line blocks are divided into J sub-blocks, such that the number of cells per sub-block is K=Z/J. If we define z=0:Z−1, then each block y=0:Y−1 contains an array of bit lines BL[y*Z+(z)]. Each sub-block j=0:J−1 of block y, contains an array of bit lines BL[y*Z+j*K+(k)], where k=0:K−1. Assuming that X and Y are even, then it follows that Z, J and K are all even. In addition, there may be a dummy/recursive memory cell at the beginning called REL[y], and RER[y] at the end of each block.


REFERENCES:
patent: 5953250 (1999-09-01), Hsu et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6459622 (2002-10-01), Ogura et al.
patent: 6469935 (2002-10-01), Hayashi

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