Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-12-15
2001-05-22
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290
Reexamination Certificate
active
06236596
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to floating gate memory devices such as EEPROMs and more specifically to a method and apparatus for reducing band-to-band currents during the erasure of flash memory devices.
BACKGROUND OF THE INVENTION
A class of non-volatile memory devices known as “flash” EEPROMs (electrically erasable programmable read only memory devices), combines the advantages of EPROM density with the electrical erasability of an EEPROM. One feature which distinguishes flash EEPROMs from standard EEPROMs is that unlike standard EEPROMs, flash EEPROMs do not contain a select transistor on a one-for-one basis with each floating gate transistor. A select transistor provides for the selection of an individual memory cell within the memory device and can be used to selectively erase a specific memory cell. Because flash EEPROMs do not contain a select transistor on a one-for-one basis with each floating gate transistor, flash EEPROM memory cells are erased in bulk, either by erasing the entire chip or by erasing paged groups of cells. Elimination of the select transistor allows for smaller cell size and gives the flash EEPROM an advantage in terms of manufacturing yield (in terms of memory capacity) over comparably sized standard EEPROMs.
Typically, a plurality of flash EEPROM cells are formed on a single semiconductor substrate (i.e. a silicon die).
FIG. 1
illustrates a single conventional flash EEPROM memory cell. As depicted in
FIG. 1
, flash memory cell
100
is formed on a P-type substrate
110
and includes an N-type double-diffused source region
102
and a N+ drain region
104
. A substrate electrode
126
is attached to substrate
110
. Drain region
104
and source region
102
are spaced apart from each other with channel region
122
interposed there between. Source electrode
114
and drain electrode
112
are respectively connected to source region
102
and drain region
104
.
The double-diffused source region
102
is formed of a lightly doped N region
128
(phosphorous doped) and a more heavily doped but shallower N+ region
130
(arsenic doped), embedded within the deep N region
128
. The phosphorous contained within N region
128
grades the source junction and thus reduces the horizontal electric (E
H
) field
134
between the source region
102
and the substrate
110
in the pn junction.
The floating gate
106
is insulatively disposed a short distance above at least one of the source and/or drain regions by a dielectric layer
118
. Above the floating gate
106
and insulatively disposed in the dielectric layer
116
, is a control gate
108
. A control gate electrode
120
is attached to control gate
108
. L
GATE
132
represents the gate length for the gates contained in flash memory cell
100
.
In a conventional method of operation, the programming of a flash EEPROM memory cell is achieved by inducing “hot electron” injections from a portion of the substrate (i.e., usually a channel section near the drain region), into the floating gate. The injected electrons carry a negative charge into the floating gate and are typically induced by grounding the source region of the substrate, biasing the control gate to a relatively high positive voltage to create an electron tracking field and biasing the drain region to a positive voltage of moderate magnitude in order to generate hot (high energy) electrons.
For example, to program flash memory cell
100
, source electrode
114
is tied to ground, drain electrode
112
is tied to a relatively high voltage (e.g. +4 volts to +9 volts) and the control gate electrode
120
is connected to a relatively high voltage level (e.g., +8 volts to +12 volts). Electrons are accelerated from source region
102
to drain region
104
and so-called “hot electrons” are generated near the drain region
104
. Some of the hot electrons are injected through the relatively thin gate dielectric layer
118
and become trapped in the floating gate
106
thereby giving floating gate
106
a negative potential.
After sufficient negative charge accumulates on floating gate
106
, the negative potential of floating gate
106
raises the threshold voltage of the stacked gate transistor and inhibits current flow through the channel
122
during a subsequent “read” mode. The magnitude of the read current is used to determine whether a memory cell has been programmed.
Conversely, to erase a flash memory device, electrons are typically driven out of the floating gate
106
by biasing the control gate
108
to a large negative voltage and the source region
102
to a low positive voltage, in order to produce a sufficiently large vertical electric field (E
V
) in the tunnel oxide. This effect happens because the floating gate
106
reaches a large negative voltage through a capacitive coupling with the control gate
108
. The sufficiently large vertical electric field (E
V
136
) in the tunnel oxide produces Fowler-Nordheim (F-N) tunneling of electrons stored in the floating gate
106
through the tunnel oxide and into the source region
102
. The charge taken from the floating gate
106
in turn produces a threshold voltage shift (V
T
shift) which can be used to deprogram (erase) the device.
For example, during erasure a relatively low positive voltage (i.e. +0.5 V to +5.0 V) is applied to source electrode
114
and a relatively large negative voltage (i.e. −7 V to −13 V) is applied to control gate electrode
120
. The voltage of substrate electrode
126
is grounded (0 V) and drain electrode
112
is allowed to float. The vertical electric field (E
V
136
) established between the control gate
108
and the source region
102
induces electrons previously stored in floating gate
106
to pass through dielectric layer
118
and into source region
102
by way of Fowler-Nordheim tunneling.
In order to produce a sufficient electric field in the tunnel oxide, it is typically necessary to bias the control gate
108
to a large enough negative voltage such that the floating gate
106
reaches a voltage of approximately −5.5 volts. A typical potential difference V
SF
between the source region
102
and floating gate
106
is on the order of 10 volts and accordingly, when the source voltage V
S
is made less positive, the control gate voltage V
CG
should be made more negative. Once the source to floating voltage V
SF
is selected, the remaining factors are preferably constrained according to the equation:
V
FG
=&agr;
CG
(V
CG
−&Dgr;V
T
)+&agr;
S
V
S
+&agr;
B
V
B
where:
V
FG
=the floating gate voltage;
V
CG
=the control gate voltage;
V
S
=the source voltage;
V
B
=the substrate or p-well bias;
&Dgr;V
T
=the threshold voltage difference arising from negative charge added to the floating gate as measured from the control gate;
&agr;
CG
=the capacitive coupling coefficient from the control gate to the floating gate;
&agr;
S
=the capacitive coupling coefficient between the source and the floating gate;
&agr;
B
=the capacitive coupling coefficient between the substrate or p-well and the floating gate.
As technology advances, a continuing goal throughout the industry is to increase the density of memory devices. By reducing the size of a flash EEPROM device a greater memory capacity can be achieved. In using more dies per wafer the cost per die can reduced. In addition, using higher density memory devices may provide for a reduction in the over all power consumption.
In order to increase the memory density of flash EEPROM devices, the memory cells are typically scaled down in size (e.g. reduction in overall footprint of the device) by reducing the gate length (L
GATE
132
) and gate width (W
GATE
138
). However, a problem with reducing the length of the memory cell gates is that the distance between the source region
102
and the drain region
104
is also reduced. As the source region
102
approaches the drain region
104
the lateral diffusion from the phosphorous in the source region (N re
Chan Vei-Han
Haddad Sameer S.
Luning Scott D.
Sobek Daniel
Thurgate Timothy James
Advanced Micro Devices , Inc.
Nelms David
Tran M.
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