Biasing circuit for UPROM cells with low voltage supply

Details Biasing circuit for UPROM cells with low voltage supply Biasing circuit for UPROM cells with low voltage supply

1997-04-30

1999-01-12

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 36518911, G11C 700

Patent

active

058597972

ABSTRACT:
A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.

REFERENCES:
patent: 5267213 (1993-11-01), Sung et al.
patent: 5422590 (1995-06-01), Coffman et al.
patent: 5642072 (1997-06-01), Miyamoto
patent: 5642073 (1997-06-01), Manning
Patent Abstracts of Japan, vol. 95, No. 003, JP-A-07 065589 (Toshiba Corp.), Mar. 10, 1995.

Affiliated with

Also associated with

Rating

Biasing circuit for UPROM cells with low voltage supply does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Biasing circuit for UPROM cells with low voltage supply, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Biasing circuit for UPROM cells with low voltage supply will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1521839