Access collision within a multiport memory

Address control for efficient memory partition

Address isolation for user-defined configuration memory in...

Apparatus and method for operating a dual port memory cell

Apparatus and method for preserving data integrity in multiple-p

Array read access control using MUX select signal gating of...

Balanced bitcell design for a multi-port register file

Bitline twisting scheme for multiport memory

Bitline/dataline short scheme to improve fall-through timing...

Block RAM having multiple configurable write modes for use...

Buffer memory arrays having nonlinear columns for providing para

Buffer using two-port memory

Bus connection circuit for read operation of multi-port...

Cell circuit for multiport memory using 3-way multiplexer

Cell circuit for multiport memory using decoder

Circuit for generating switching control signal

Clock driver and boundary latch for a multi-port SRAM

Clock generator for pseudo dual port memory

Clock generator for pseudo dual port memory

Clock-gated model transformation for asynchronous testing of...