Array read access control using MUX select signal gating of...

Details Array read access control using MUX select signal gating of... Array read access control using MUX select signal gating of...

2007-03-06

2007-03-06

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S230060, C365S154000

Reexamination Certificate

active

10965626

ABSTRACT:
An apparatus, a method, and a computer program product are provided for time reduction for an array read access control consisting of a bitcell with logic gating and a pull down device included, therein. To reduce gate delay this design implements gating logic inside the bitcell. The multiplex select gating signals are brought into the bitcell, and are gated with the data array. The gating logic controls the pull down device, and MUX select signals can be produced as a readout of the bitcell. This design reduces gate delay because the dependency upon the gating logic is overridden and the number of stages is reduced.

REFERENCES:
patent: 5790454 (1998-08-01), Choi
patent: 2002/0196667 (2002-12-01), Ikehashi et al.

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