Bitline/dataline short scheme to improve fall-through timing...

Details Bitline/dataline short scheme to improve fall-through timing... Bitline/dataline short scheme to improve fall-through timing...

2000-09-29

2002-10-29

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000, C365S190000, C365S204000, C365S220000, C365S221000, C365S239000

Reexamination Certificate

active

06473357

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for improving fall-through timing in a multi-port memory generally and, more particularly, to a method and/or architecture for implementing a bitline/dataline short to improve fall-through timing in a multi-port memory.
BACKGROUND OF THE INVENTION
In a conventional dual port memory, the read port access time is slowed down when data has to be written into a memory cell before data can be read from the memory cell. Similarly, a read operation in a conventional first in, first out (FIFO) memory is delayed when the write port accesses the same memory cell address as the read port. The dual port memory fall-through access time and the FIFO fall-through empty flag skew time are increased because of the write before read delay.
Referring to
FIG. 1
, a schematic diagram illustrating a conventional six transistor (6-T) memory cell
10
is shown. The memory cell
10
includes a NMOS transistor
12
, a NMOS transistor
14
, an inverter
16
, and an inverter
18
. The memory cell
10
also includes a write bitline WBL, a write wordline WWL, a read wordline RWL, and a read bitline bar RBLB. An NMOS transistor
20
external to the circuit
10
couples the write bitline bar WBLB to the read bitline bar RBLB in response to a signal SHORT. The NMOS transistors
12
and
14
are configured as pass gates.
Referring to
FIG. 2
, a block diagram of a circuit
30
illustrating a conventional FIFO memory is shown. The circuit
30
is shown as a single ended implementation. However, the description of the circuit
30
fall-through time is also applicable to a conventional dual ended memory design. The circuit
30
has a write data path circuit
32
, a memory array
34
, a read data path circuit
36
, a read/write equal (WREQ) logic circuit
38
, and a local short logic circuit
40
.
A FIFO can have a dedicated read port and a dedicated write port. The memory array
34
can include a plurality of the 6-T memory cell memory cells implemented similarly to the
10
of FIG.
1
. Fall-through timing is slowed when the write port
32
has the same address as the read port
36
. The read port
36
access time will be slowed down. because the data has to be written into the memory cell
10
before the data can be read out.
A specific time is needed to write into a memory cell
10
(i.e., a write-through time). An additional time is needed to read out of the memory cell
10
. The actual time taken to perform both the write and then the read operation at the particular memory cell can be lengthy. The specification for the operation to write to and read from the same memory cell simultaneously (i.e., the fall-through time) is always a longer time than the specification for a read operation where no writing is involved. The fall-through time of a conventional memory can be twice as long as the normal read access time.
To overcome the above problem, the WREQ logic circuit
38
compares a read pointer RADDRESS and a write pointer WADDRESS. The WREQ logic circuit
38
generates a signal ROW_MATCH when the write address and the read address are pointing to the same row. The local short logic circuit
40
generates the signal SHORT in response to the signals ROW_MATCH and COL_ADDRESS. The signal SHORT switches on the transistor
20
in a selected column to short (couple) the write bitline bar WBLB with the read bitline bar RBLB. Any time there is a row address match, the write bitline bar WBLB and the read bitline bar RBLB of the memory cells
10
in the selected column are shorted together. The read address and the write address are not necessarily the same address when the row address matches since the column addresses can be different. However, the signal SHORT only affects the bitlines, and not the data lines. Additionally, the signal SHORT is only active when the row addresses match.
It would be desirable to implement a method and/or architecture that reduces fall-through time and/or logic overhead.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a memory array having a first port and one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a bitline/dataline short to improve fall-through timing in a multi-port memory that may (i) speed up the fall-through access time in multi-port memories, (ii) reduce array switching activity in FIFOs, (iii) short bitlines and data lines only when the same memory cell is addressed, (iv) use existing dual port arbitration logic to control bitline and dataline shorting, (v) eliminate write/read equality (WREQ) logic, (vi) reduce current during memory access, (vii) eliminate unnecessary bitline switching, (viii) be implemented in an embedded block and/or stand-alone chip designs, and/or (ix) reduce crowbar currents.


REFERENCES:
patent: 4580245 (1986-04-01), Siegler
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 5253207 (1993-10-01), Shikatani
patent: 5673234 (1997-09-01), Hawkins et al.
patent: 5790461 (1998-08-01), Holst
patent: 5862092 (1999-01-01), Hawkins et al.
patent: 5894432 (1999-04-01), Lotfi

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