Address control for efficient memory partition

Details Address control for efficient memory partition Address control for efficient memory partition

2006-06-06

2006-06-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S230010, C365S230020, C365S189040, C365S189120

Reexamination Certificate

active

07057962

ABSTRACT:
A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

REFERENCES:
patent: 5325332 (1994-06-01), Tagaya

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