Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2002-10-17
2004-11-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Multiple port access
C365S189020
Reexamination Certificate
active
06826110
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a multiport memory and, more particularly, to an improved cell circuit for data readout for use in a multiport memory.
2. Description of the Related Art
Current microelectronic circuits will achieve complicated systems with a great number of transistors, and the number will keep increasing in the future. Generally, these systems include a plurality of cooperating subsystems for processing data. One apparent problem with realizing these systems is the storage of the data to be processed, as well as their data processing programs. The most powerful systems will surely be realizable if a memory is available to which the subsystems can gain access chronologically parallel and with a high bandwidth. Such memories, which have multiple ports as external terminals, to which the external component units can gain access chronologically parallel, are generally known as multiport memories.
A prior-art multiport memory generally uses a large multiplexer to select one of a plurality of data store cell outputs. This multiplexer requires the same number of select signals as that of the data store cell outputs. Typically, this translates into the same number of read wordlines each carrying a single select signal. For example, if a memory block requires an 8:1 multiplexer, eight select signals are required for controlling the multiplexer. In this example, a prior-art cell circuit would have eight read wordlines for carrying the eight select signals to the multiplexer from outside the memory array. Under this circuit design, the number of read wordlines-eight in this example-would require too much space, since adding each read wordline generally requires large space. Also, there are other concerns relating to having a large number of read wordlines such as power consumption in the memory array. These space and/or power concerns become more and more relevant and legitimate in designing a memory array, as the capacity of a memory dramatically increases.
Therefore, a need exists for a multiport memory with an improved readout cell configuration that takes up less space for a readout cell area by reducing both the readout cell area and the number of read wordlines.
SUMMARY OF THE INVENTION
The present invention provides a cell circuit for data readout in a memory block of a multiport memory array. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, a decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals.
In one aspect of the invention, a multiplexer is coupled to the decoder. The multiplexer receives the select signals and selects one of the write data signals based on the select signals.
In another aspect, a plurality of read wordlines is coupled to the decoder for carrying the subset of the address inputs to the decoder.
REFERENCES:
patent: 5657291 (1997-08-01), Podlesny et al.
patent: 6166963 (2000-12-01), Wen
patent: 6212122 (2001-04-01), Wen
patent: 6594194 (2003-07-01), Gold et al.
Dhong Sang Hoo
Hofstee Harm Peter
Onishi Shoji
Takahashi Osamu
Carr LLP
Carwell Robert M.
Phung Anh
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