Static information storage and retrieval – Addressing – Multiple port access
Patent
1998-05-21
1999-11-09
Mai, Son
Static information storage and retrieval
Addressing
Multiple port access
36518904, 711131, 711149, G11C 800
Patent
active
059827009
ABSTRACT:
Tri-port memory buffers having fast fall-through capability contain a custom tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. In particular, a preferred tri-port memory array is provided having a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports. Efficient steering circuitry is also preferably provided as a bidirectional crosspoint switch to electrically couple terminals (lines IO and IOB) of the bidirectional input/output port in parallel to bit lines (BL and BLB) in the supplemental memory array during a write-to-memory time interval and vice versa during a read-from-memory time interval. Circuitry is also preferably provided for controlling operation of the tri-port and supplemental memory arrays so that to the outside world the buffer memory device appears to have all the capacity of the large and highly integrated supplemental memory array, and all the most preferred features and functionality such as extremely fast fall-through capability of conventional dual-port buffer memory devices of more limited capacity.
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Integrated Device Technology Inc.
Mai Son
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