Clock generator for pseudo dual port memory

Details Clock generator for pseudo dual port memory Clock generator for pseudo dual port memory

2003-03-25

2004-10-26

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S189040

Reexamination Certificate

active

06809983

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the field of memory timing, and particularly to a circuit and method for generating clock signals for a pseudo dual port memory.
BACKGROUND OF THE INVENTION
Dual or multi port memory is usually much lower density than single port memory because of the core cell structure. To increase the dual (multi) port memory density, pseudo dual port memory can be used. Although the external operation of pseudo dual port memory resembles the operation of true dual port memory, pseudo dual port memory incorporates a single port core cell. Pseudo dual port memory should perform multiple read and/or write operations within a single clock cycle. The timing is achieved through the use of one clock.
The dual port memory timing circuit of
FIG. 4
works well at slower clock speeds, but is insufficient for higher clock soon to be achieved for input/output data transfers to a pseudo dual port memory. The clock signal is delayed for both read and write operations to allow sufficient set up and hold times for data. The rising edge of CLK generates the first ICLK for A port operation with ENA through Q
1
and Q
2
. The falling edge of CLK generates the next ICLK for B port operation with ENB through Q
3
and Q
4
. The read operation usually occurs by the first ICLK and the write operation usually occurs by the next ICLK. These ICLKs depends on the ENA and ENB status.
Pseudo dual port memory needs two operations—read and write operations—in one clock cycle. If the clock rising edge and falling edge are used to initiate these two operations, a first consideration is clock cycle time. Clock cycle time is set to at least twice the length of the longer cycle time in each port. The second consideration is clock duty ratio. If the clock falling edge is used for the other operation, the clock duty ratio should be included in the longer cycle time. The clock duty ratio effectively acts as a bottleneck for the higher cycle time operation.
Therefore, it would be desirable to provide a circuit and method to synchronize the write and read clock signals for a pseudo dual port memory.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a circuit and method for preventing signal degradation for a clock signal supplied to a pseudo dual port memory.
In a first aspect of the present invention, a circuit for improving timing signal integrity for a pseudo dual port memory includes a first circuit for generating a first pulse of a first timing signal and a second circuit for receiving the first timing signal as an input to generate a second pulse from the first timing signal.
In a second aspect of the present invention, a method is disclosed for providing a clock signal to a pseudo dual port memory. In the method, a first signal is received that has a periodicity, the first signal having a clock rising edge, a high logic level, a clock falling edge, and a low logic level. A second received signal controls data transfer operations. The second signal has a pulse that activates a circuit for providing a clock signal to a dual port memory. A read clock signal is generated for a first port. The read clock signal is used to generate a write clock signal for a second port. Alternatively, the first and second port may be combined into a pseudo dual port.
Several advantages are provided by the present invention. An advantage is that the port B (write) clock ICLKB is not related to CLK falling edge. The port B clock ICLKB is generated after A (read) port operation by the RESET signal that is generated by a timing block (e.g. a self time block) or some other control block. The port B clock ICLKB will make B port (write) operation start just after A (read) port operation regardless of CLK falling edge. Other advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. The port B address and input data can be latched with sufficient set up and hold times by using ICLKB as a feedback control and the delaying effect of other circuit elements.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.


REFERENCES:
patent: 5375089 (1994-12-01), Lo
patent: 6166963 (2000-12-01), Wen
patent: 6430088 (2002-08-01), Plants et al.
patent: 6590826 (2003-07-01), Sawyer

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