Bus connection circuit for read operation of multi-port...

Details Bus connection circuit for read operation of multi-port... Bus connection circuit for read operation of multi-port...

2006-05-16

2006-05-16

Tran, Michael (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S191000

Reexamination Certificate

active

07046575

ABSTRACT:
There is provided a semiconductor memory design technique, specifically a bus connection circuit for a read operation of a multi-port memory device. The bus connection circuit is adapted to a current sensing type bus transmission/reception structure. The bus connection circuit includes: a read data sensing/latching unit for sensing/latching a read data applied on a local data bus in response to a read data strobe signal; and a read data driving unit for driving the data latched in the read data sensing/latching unit to a global data bus in response to a read data driving pulse, and for connecting or disconnecting a path of current flowing the global data bus according to a logic level of the latched data.

REFERENCES:
patent: 5835436 (1998-11-01), Ooishi
patent: 5991223 (1999-11-01), Kozaru et al.
patent: 6104653 (2000-08-01), Proebsting
patent: 6163475 (2000-12-01), Proebsting
patent: 6185256 (2001-02-01), Saito et al.

Affiliated with

Also associated with

Rating

Bus connection circuit for read operation of multi-port... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bus connection circuit for read operation of multi-port..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus connection circuit for read operation of multi-port... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3545691