Balanced bitcell design for a multi-port register file

Details Balanced bitcell design for a multi-port register file Balanced bitcell design for a multi-port register file

2007-08-27

2010-02-02

Lane, Jack A (Department: 2185)

Static information storage and retrieval

Addressing

Multiple port access

C365S051000, C365S063000, C365S154000, C365S189030, C365S189050, C365S190000, C365S202000, C365S206000, C365S214000, C365S230060, C711S149000

Reexamination Certificate

active

07656739

ABSTRACT:
In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

REFERENCES:
patent: 5289427 (1994-02-01), Nicholes et al.
patent: 5642325 (1997-06-01), Ang
patent: 5812486 (1998-09-01), Shinmori
patent: 6519178 (2003-02-01), Alvandpour et al.

Affiliated with

Also associated with

Rating

Balanced bitcell design for a multi-port register file does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Balanced bitcell design for a multi-port register file, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Balanced bitcell design for a multi-port register file will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4197167