Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2000-05-19
2002-04-16
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C711S142000, C711S143000, C711S149000
Reexamination Certificate
active
06373779
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to dedicated block random access memory (RAM) located on a programmable logic device, such as a field programmable gate array (FPGA).
RELATED ART
FPGAs typically include an array of configurable logic blocks (CLBs), input/output blocks (IOBs) and programmable interconnect circuitry that extends between the CLBs and IOBs. Some FPGAs include dedicated columns of block RAM which are located between columns of the CLBs. Such block RAM provides a relatively high-density memory. In the absence of the block RAM, memory could be provided by configuring the CLBs in an appropriate manner. However, a relatively large number of CLBs are required to provide a small memory, thereby resulting in an inefficient use of FPGA resources. An FPGA that includes block RAM is described in U.S. Pat. No. 5,933,023.
The block RAMs present in the above-identified FPGAs are dual-port block RAMs having a single write mode. When a data value is written to a memory cell, that data value appears as an output of the block RAM. This write mode is referred to as a “write with write-back” mode. While the write with write-back mode is useful, the dual-port block RAMs of conventional FPGAs have undesirably been limited to a single write mode. Providing for multiple write modes would advantageously provide the user with more flexibility to suit their application needs.
It would therefore be desirable to have a dual-port block RAM with a plurality of selectable write modes.
SUMMARY
Accordingly, the present invention provides an FPGA that includes block RAM having a plurality of selectable write modes. The block RAM includes a memory cell array and control logic that is configurable to select one of a plurality of write modes for accessing the memory cell array. In one embodiment, the write modes include a write with write-back mode, a write without write-back mode, and a read then write mode. The control logic selects the write mode in response to configuration bits stored in corresponding configuration memory cells of the FPGA. The configuration bits are typically programmed during configuration of the PLD.
In a particular embodiment, the block RAM is a dual-port memory having a first port and a second port. In this embodiment, the first and second ports can be independently configured to have different (or the same) write modes. The widths of the first and second ports can also be independently configured.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5230045 (1993-07-01), Sindhu
patent: 5249159 (1993-09-01), Sato
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5659709 (1997-08-01), Quach
patent: 5933023 (1999-08-01), Young
patent: 6049487 (2000-08-01), Plants et al.
patent: 6097664 (2000-08-01), Nguyen et al.
patent: 6104663 (2000-08-01), Kablanian
patent: 6122218 (2000-09-01), Kang
patent: 6138211 (2000-10-01), Ahn et al.
“The Programmable Logic Data Book”, Sep. 1996; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124; pp. 4-14 to 4-20.
Pang Raymond C.
Young Steven P.
Ho Hoai V.
Hoffman, Esq. E. Eric
Xilinx , Inc.
Young Edel M.
LandOfFree
Block RAM having multiple configurable write modes for use... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Block RAM having multiple configurable write modes for use..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Block RAM having multiple configurable write modes for use... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2917701