Bitline twisting scheme for multiport memory

Details Bitline twisting scheme for multiport memory Bitline twisting scheme for multiport memory

2005-08-01

2008-08-19

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S069000, C365S154000

Reexamination Certificate

active

07414913

ABSTRACT:
A multiport memory in one embodiment of the invention includes a memory cell array, where each column in the array has two exterior complementary bitline pairs and zero, one, or more interior complementary bitline pairs. Across each pair of adjacent columns in the array, the adjacent exterior bitline pairs are associated with the same port in the multiport memory. In addition, within each column, the two exterior bitline pairs have the same, non-zero number of crossovers, and, across each pair of adjacent columns, the exterior bitline pairs have different numbers of crossovers. Furthermore, each column has at least one reference signal line located between the two exterior bitline pairs.

REFERENCES:
patent: 5287322 (1994-02-01), Rastegar
patent: 5818786 (1998-10-01), Yoneda
patent: 6084820 (2000-07-01), Raszka
patent: 6370078 (2002-04-01), Wik et al.
patent: 6445638 (2002-09-01), Hsu et al.
patent: 6498758 (2002-12-01), Pomar et al.
patent: 6665204 (2003-12-01), Takeda
U.S. Appl. No. 10/671,756, filed Sep. 26, 2003.

Affiliated with

Also associated with

Rating

Bitline twisting scheme for multiport memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Bitline twisting scheme for multiport memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bitline twisting scheme for multiport memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3998818