Cell circuit for multiport memory using 3-way multiplexer
Cell circuit for multiport memory using decoder
Circuit for generating switching control signal
Clock driver and boundary latch for a multi-port SRAM
Clock generator for pseudo dual port memory
Clock generator for pseudo dual port memory
Clock-gated model transformation for asynchronous testing of...
CMOS memory cell
Combination dual-port random access memory and multiple first-in
Compact decode and multiplexing circuitry for a multi-port...
Compact decode and multiplexing circuitry for a multi-port...
Compact decode and multiplexing circuitry for a multi-port...
Compact decode and multiplexing circuitry for a multi-port...
Compensation capacitance for minimizing bit line coupling in...
Configurable random-access-memory circuitry
Configurable SRAM for field programmable gate array
Controller for dual ported memory
Converting dual port memory into 2 single port memories