Buffer using two-port memory

Details Buffer using two-port memory Buffer using two-port memory

2003-01-09

2004-07-06

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189120, C365S230060

Reexamination Certificate

active

06760273

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a buffer using a two-port memory. More particularly, the present invention relates to a buffer with a two-port memory, which aims at a high-speed access time when being used as a buffer.
In the related art, two-port RAMs each having a first port acting as a write port and a second port acting as a read port are quoted. The two-port RAM is used as a buffer that counts up an address value in each port with a corresponding strobe signal, stores sets of data arrived for a given period, and transmits each set of data in the arrival order in accordance with a request.
The RAM includes an address decoder, memory cells arranged two-dimensionally, a signal amplifier circuit corresponding to writing, and a signal amplifier circuit corresponding to reading. The RAM specifies a line of memory cells corresponding to a specific address specified by the address decoder. One of drive lines (called a word line) provided for respective lines of memory cells is activated to select the memory cells on the selected line.
That process is performed by a three-step procedure. That is, the three-step procedure includes the steps of reading an address value from an address register every time a memory cell is accessed, decoding the address until a word line driven from the address value is specified, and driving only one word line to an active state. In the steps, the sum of respective delay times represents an access time to a memory cell.
FIG. 6
is a block diagram illustrating a related-art buffer using a two-port RAM. A memory cell array
10
, which includes memory cells arranged two-dimensionally (in a matrix form), forms a storage element area. In order to access a specific memory cell in the memory cell array
10
, column selection lines (generally called word lines) and row selection lines (generally called bit lines) are arranged in a matrix form. Generally, one of the word lines is specifically activated by the address provided to the RAM. The associated bit line transmits data provided to the RAM, to a memory cell.
Referring to
FIG. 6
, the RAM has one read port and one write port. The two-ports can operate simultaneously and independently. The two-port RAM includes n word lines (
51
_
0
,
51
_
1
,
51
_
2
, . . . ,
51
—
n−
1,
51
—
n
) corresponding a write address, n word lines (
71
_
0
,
71
_
1
,
71
_
2
, . . . ,
71
—
n−
1,
71
—
n
) corresponding to a read address, a bit line
21
corresponding to write data, and a bit line
31
corresponding to read data.
FIG. 6
shows one bit line
21
for write data and one bit line
31
for read data. However, there are actually bit lines corresponding to the number of bits. Generally, the differential transmission is performed that transmits one bit using a pair of bit lines for positive logic and negative logic. Actually, the number of bit lines is twice the number of bits.
Next, the operation of the conventional buffer having a two-port RAM shown in
FIG. 6
will be explained below.
First, an initial value, being generally all 0 data, is set to the write address register
600
. However, a certain value may be set as an initial value to set an offset starting a write operation from a specific address. Here, it is assumed that all 0 data are set to the write address register. Each of the write address decoders (
640
_
0
,
640
_
1
,
640
_
2
, . . . ,
640
—
n−
1,
640
—
n
) decodes the address value set to the write address register
600
. Only the address decoder in coincidence with an address value outputs an active result. In the initial state where the address value is of all 0s, only the address decoder (
640
_
0
) corresponding to the least significant address outputs an active result.
The word line drivers (
50
_
0
,
50
_
1
,
50
_
2
, . . . ,
50
—
n−
1,
50
—
n
) respectively reinforce the drive capability of the outputs of the write address decoders (
640
_
0
,
640
_
1
,
640
_
2
, . . . ,
640
—
n−
1,
640
—
n
) and then drive the word lines (
51
_
0
,
51
_
1
,
51
_
2
, . . . ,
51
—
n−
1,
51
—
n
). Actually, only the word line connected to the address decoder outputting an active result is driven. In an initial state, only the word line (
51
_
0
) driven by the word line driver (
50
_
0
) corresponding to the least significant address becomes a valid selection state.
On the other hand, the write data stored in the write data register
20
is sent to each memory cell through the bit line
21
. In the initial state, since the word line (
50
_
0
) corresponding to the least address is in a selection state, the data in the write data register
20
is written into the memory cell of the least significant address.
The incrementer
601
, connected to the output of the write address register
600
, counts up the address. The count-up address value is again fed back to the input of the write address register
600
. The write address register
600
captures the count-up address only when the strobe signal
42
is in an active state. When the strobe signal
42
is not an active state, the write address register
600
continues to hold the counted-up value. Therefore, only when the strobe signal
42
is in an active state, the write address value is counted up. At the same time, the strobe signal
42
controls the data capture to the write data register
20
. Simultaneously when the write address value is counted up, a new write data value is captured into the write data register
20
.
In doing so, when the strobe signal
42
is in an active state, the write address value is counted up. As a result of address decoding, the word line driven to an effective selection state is sequentially changed in the increasing order from the least significant address. At the same time, since the write data is updated sequentially, newer write data is stored into an upper address. At the time when the write address value becomes an all “1s” state, the status reaches the most significant address. Thereafter, when being counted up with the strobe signal, the write address value is reset to an all “0s” state, so that the data of the least significant address is overwritten. Thus, the ring data buffer that can store sets of data corresponding to the number of addresses of the RAM is configured.
That is also the case for the operation of the reading side. After the address value stored in the read address register
650
is decoded by the read address decoders (
660
_
0
,
660
_
1
,
660
_
2
, . . . ,
660
—
n−
1,
660
—
n
), the word lines (
71
_
0
,
71
_
1
,
71
_
2
, . . . ,
71
—
n−
1,
71
—
n
) are respectively driven through the word line drivers (
70
_
0
,
70
_
1
,
70
_
2
, . . . ,
70
—
n−
1,
70
—
n
). As a result, data in the memory cell of a corresponding address is read out and is input to the read data register
30
through the bit line
31
. The incrementer
651
, connected to the output of the read address register
650
, counts up the read address. When the strobe signal
62
is in an active state, the incrementer
651
updates the content of the read address register
650
and the content of the read data register
30
. In doing so, when the strobe signal is in an active state on the reading side, the data stored in the memory cells are sequentially read out to upper addresses from the least significant address. After the data of the most significant address is read out, the operation returns to the least significant address to read data again.
As described above, in the operation of the conventional buffer using a two-port memory, the writing side is first operated to store data to memory cells. After it is ascertained that data have been stored until a specified address, the operation of the reading side begins. When the operation of the reading side begins, the buffer is controlled using only the strobe signal
42
on the reading side and the strobe signal
62
on the writing side.
However, in the above-mentioned buffer (with a two-port RAM), only by sequentially counting up the read address or the write address with the s

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