Bi-layer approach for a hermetic low dielectric constant...
Bi-layer capping of low-K dielectric films
Bi-layer etch stop for inter-level via
Bi-layer etch stop process for defect reduction and via...
Bi-layer floating gate for improved work function between...
Bi-layer photoresist method for forming high resolution...
Bi-layer resist process
Bi-layer resist process for dual damascene
Bi-layer silicon film and method of fabrication
Bi-layer trim etch process to form integrated circuit gate...
Bi-level resist structure and fabrication method for contact...
Bi-level resist structure and fabrication method for contact...
Bi-modal halo implantation
Bias plasma deposition for selective low dielectric insulation
Biased H 2 etch process in deposition-etch-deposition gap fill
Biased pulse DC reactive sputtering of oxide films
Biased pulse DC reactive sputtering of oxide films
Biased pulse DC reactive sputtering of oxide films
Biased, triple-well fully depleted SOI structure, and...
BiCMOS integration scheme with raised extrinsic base