Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2003-02-04
2004-08-24
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S758000
Reexamination Certificate
active
06780782
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a method of fabricating integrated circuits and other electronic devices on semiconductor substrates. More particularly, the invention relates to an improved process for forming contact holes on semiconductor substrates.
(2) Description of the Related Art
In the fabrication of semiconductor integrated circuits multilevel integration structures are used to connect the various devices in the circuits. As circuit density increases very large scale integration (VLSI) and ultra-large scale integration (ULSI) are used to interconnect the devices in integrated circuits fabricated on semiconductor substrates and the feature sizes of device components have decreased to 0.1 micron and less. This is particularly true for the contact holes required to connect devices between levels in multilevel structures. Therefore, fabrication processes for achieving VLSI and ULSI levels of integration must be capable of reliably forming contact holes between successive levels, where the contact holes have dimensions of the order of 0.1 micron or less in diameter.
An important challenge in the fabrication of multilevel integrated circuits on semiconductor substrates is to develop masking and etching technologies which allow reliable formation of semiconductor devices, interconnection conducting patterns, and interlevel contact holes which have dimensions of 0.1 micron on less. The masking technologies and the etching technologies must be compatible and result in high fabrication process yield and minimum process cost. In order to minimize cost, fabrication tool throughput must be maximized. Therefore, sequential processing in the same fabrication tool, without necessity to transfer to additional tools, is desirable and leads to reduced product cost.
As device feature size is reduced to 0.1 micron and less, the ability to achieve good image resolution in high density, small pitch patterns requires that the photo resist exposure and imaging processes be performed on a thin photo resist imaging layer. However, when etching features in thick layers, such as ILD (Inter-Level Dielectric) layers, thin photo resist masks are inadequate and schemes to provide more robust masking layers are required.
Numerous patents disclose bi-level resist masking structures in order to achieve greater dimensional fidelity in the desired integration pattern. For example, U.S. Pat. No. 5,227,280 entitled “Resists With Enhanced Sensitivity And Contrast” granted Jul. 13, 1993 to James A. Jubinsky et al. describes a bi-level resist structure and method of fabrication. The method forms a bi-level resist structure for use in lift-off processes wherein the underlayer comprises a photo resist layer with an admixture of cyclic anhydrides and the top layer comprises a photo resist layer.
Also, U.S. Pat. No. 5,286,607 entitled “Bi-Layer Resist Process For Semiconductor Processing” granted Feb. 15, 1994 to Andrew V. Brown shows a method of forming a resist mask on a substrate in which a planarizing polymer layer is first formed on the substrate. Then the planarizing polymer layer is exposed to a silicon containing medium, so as to cause silicon from the medium to penetrate the top portion of the planarizing polymer layer. Next a resist layer is formed over the first layer, exposed and developed to form a pattern and then RIE is used to remove the exposed areas of the first layer including the silicon that penetrated the first layer. Finally RIE in an oxygen plasma removes the resist layer while etching through the planarizing polymer in the exposed areas.
And, U.S. Pat. No. 5,545,512 entitled “Method Of Forming A Pattern Of Silylated Planarizing Photoresist” granted Aug. 13, 1996 to Tatsuo Nakato describes a multilayer photo resist process, wherein a mask pattern of silicon dioxide is formed on the surface of a layer of photo resist. The steps in the method include irradiating the surface of a photo resist layer to create a unpatterned silicon-reactive region adjacent to the surface of the photo resist. The next step is to soft bake the irradiated photo resist in a silicon containing environment to convert the silicon-reactive region to a silicon-enriched region adjacent to the surface of the photo resist. A patterned layer of photo resist is then formed overlying the silicon-enriched region and an etching step transfers the mask pattern to the silicon-enriched region of the photo resist. The remaining areas of the silicon-enriched layer are exposed to an oxygen plasma which converts the silicon-enriched areas to silicon dioxide.
Also, U.S. Pat. No. 5,427,649 entitled “Method For Forming A Pattern By Silylation” granted Jun. 27, 1995 to Cheol-hong Kim et al. describes a method for forming a mask pattern by forming a first photo resist layer having a silylated surface. Then, a second photo resist layer is formed on the silylation layer, which is then exposed and developed to form a pattern in the second photo resist layer. The pattern in the second photo resist layer is used to etch a pattern in the silylated first photo resist layer. The silylation pattern is then oxidized. Next, the first photo resist layer is etched using the oxidized silylation pattern as a mask.
Also, U.S. Pat. No. 6,218,292 B1 entitled “Dual Layer Bottom Anti-Reflective Coating” granted Apr. 17, 2001 to David K. Foote describes a method of manufacturing a semiconductor device wherein a first anti-reflective coating is deposited on a substrate followed by depositing a second anti-reflective coating on the first anti-reflective coating.
Also, U.S. Pat. No. 6,057,587 entitled “Semiconductor Device With Anti-Reflective Structure” granted May 2, 2000 to Kouros Ghandehari et al. reveals an anti-reflective structure for use in patterning metal layers on semiconductor substrates.
Also, U.S. Pat. No. 6,037,276 entitled “Method For Improving Patterning Of A Conductive Layer In An Integrated Circuit” granted Mar. 14, 2000 to HuaTai Lin et al. shows a lithographic patterning process on a conductive layer wherein an oxynitride layer is formed on the conductive layer, a nitride layer is formed on the oxynitride layer, and a photoresist layer is formed on the nitride layer.
Further, U.S. Pat. No. 6,147,007 entitled “Method For Forming A Contact Hole on a Semiconductor Wafer” granted Nov. 14, 2000 to Chan-Lon Yang et al. describes a process for etching a contact hole in silicon oxide using a patterned photo resist layer as a mask. A silicon nitride layer is used as an etch stop when etching through a silicon oxide layer.
When circuit density requires that contact holes be of the order of 0.1 micron or less in diameter, resist masking schemes which use a single organic ARC (anti-reflection coating) layer or a single inorganic ARC layer are not adequate. Such single layer ARC schemes result in irregularly shaped etched holes having severe striations which can then contribute to shorting between adjacent contact holes.
Also, when using a bi-level resist structure, comprising a top imaging layer and a bottom dry developed organic layer, as the mask for plasma etching holes in silicon oxide using conventional gaseous mixtures of C
X
F
Y
, argon, and O
2
the top imaging layer is not removed by the silicon oxide etch process and a residue forms on the top of the top imaging layer during the etching of the silicon oxide. This residue further impacts the successful removal of the top imaging layer by subsequent O
2
ashing processes and degrades the fabrication process yield.
The present invention is directed to an improved method of etching very small contact holes through dielectric layers used to separate patterned conducting layers in multilevel integrated circuits formed on semiconductor substrates. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which can be used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. Contact holes formed using this improved method may be use
Hsu Ju Wang
Tao Hun-Jan
Tsai Ming-Huan
Wu Tsang Jiuh
Haynes and Boone LLP
Nhu David
Taiwan Semiconductor Manufacturing Company , Ltd.
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