Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-10
2003-05-20
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S692000, C438S723000, C438S724000, C438S740000, C438S750000, C438S704000, C438S734000
Reexamination Certificate
active
06566258
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor integrated circuits and methods of fabricating them. In particular, the invention relates to the structure and fabrication of inter-level metallizations, such as vias.
BACKGROUND ART
Large, advanced semiconductor integrated circuits typically contain a large number of metallization levels to allow for the complex electrical interconnects required for the millions of semiconductor devices included in such silicon integrated circuits. One wiring technology, called dual damascene, has been recently developed and offers many advantages. Two metal levels of such a structure are schematically illustrated in cross section in
FIG. 1. A
substrate
10
may be the underlying silicon substrate including the semiconductor devices or may be a yet lower wiring level. A first metal layer includes a lower stop layer
12
, a lower dielectric layer
14
, a middle stop layer
16
, and an upper dielectric layer
14
. As exemplary materials, the two dielectric layers
14
,
18
are composed of silicon dioxide, and the stop layers
12
,
16
are composed of silicon nitride.
There are various methods of forming the inter-level metallization, but for convenience the counterbore method will e described. This process is described in more detail by Tang et al. in U.S. Pat. No. 6,380,096, filed Nov. 30, 1998, incorporated herein by reference in its entirety. The three four layers
12
,
14
,
16
,
18
are deposited as unpatterned layers. In one photolithographic step, one of more deep, narrow via holes are etched from the top of the upper dielectric layer
18
through the upper stop layer
16
and the lower dielectric layer
14
to stop on the lower stop layer
12
overlying the substrate
10
. The width of the via may be 0.18 &mgr;m or less while its depth may be approximately half of the approximately 1.2 &mgr;m-thick inter-level dual dielectric layers. That is, it has an aspect ratio of at least three and often more. In a second photolithographic step, a wide but shallow trench is etched through the upper dielectric layer
14
to connect with the one or more via holes, which are now shorter than originally. The second etching step is performed with a chemistry that does not etch the two stop layers
12
,
16
. A short anisotropic etch is used to remove the lower stop
12
exposed at the bottom of the via hole. Thereafter, a single deposition sequence fills both the remaining portion of the deep via hole and the trench with a metal
22
which both acts as a via
24
for the narrow electrical contact to the underlying layer
10
and a horizontal interconnect
24
in the trench area. The metal deposition initially forms over the top of the upper dielectric layer
18
, but chemical mechanical polishing (CMP) is used to remove the portion of the softer metal extending above and outside the trench
24
.
A second metal level is similarly formed in the same manner with a lower stop layer
30
, a lower dielectric layer
32
, a middle upper stop layer
34
, and an upper dielectric layer
36
. A metal layer
38
forms a via
40
and trench interconnect
42
. The via
40
of the upper metal level electrically connects to the trench interconnect
24
of the lower metal level.
Dual damascene is particularly useful with copper metallization since no copper etching is required. Copper offers both decreased resistance and lower electromigration. The copper metallization, however, is deposited in a somewhat involved process. Typically, a thin barrier layer of, for example, Ta/TaN is deposited to prevent the copper in the metallization and the silica-based dielectric from intermixing. Then, a thin copper seed layer is coated onto the sides and bottom of the high aspect-ratio holes. The remainder of the metallization is deposited by electrochemical plating (ECP). The copper seed layer both acts as an electrode for the plating and nucleates the growth of the ECP copper. The chemical mechanical polishing of the copper after the copper fill removes from the top of the upper dielectric layer not only the copper outside of the hole but also the barrier layer and any non-oxide layer, such as an anti-reflection coating (ARC) formed over the upper dielectric layer.
The Cu seed layer deposition is preferably performed by self-ionized plasma (SIP) sputtering, as described by Fu et al. in U.S. Pat. No. 6,183,614, filed Aug. 12, 1999, by Chiang et al. in U.S. Pat. No. 6,348,929 filed Oct. 8, 1999, and by Fu et al. in U.S. Pat. No. 6,306,265, filed Apr. 11, 2000, all incorporated herein by reference in their entireties. SIP uses a variety of techniques to ionize a large fraction of the sputtered copper atoms and to accelerate them to the wafer in a low-pressure process. Thereby, the copper atoms approach the wafer nearly perpendicularly and travel deep within the narrow holes. Fu et al. describe an improved version called SIP
+
in U.S. Pat. No. 6,277,249. This method uses a sputtering target having an annular vault rising above a generally planar face and the magnetron includes magnets arranged around the walls of the vault. The vault may alternatively be viewed as an inverted annular trough. The Ta/TaN deposition may be performed by SIP sputtering, by a combination of SIP sputtering and chemical vapor deposition (CVD), by ionized metal plating (IMP) using high-density plasma (HDP) sputtering or by other methods.
However, problems arise with the process and structure as described above. The upper level via
40
may not be precisely aligned with the lower level trench
24
. As a result, a via
40
positioned near the edge of the underlying trench
24
may be unlanded so that an overhang
46
is formed in which the via
40
of the second metal level overlies the upper dielectric layer
18
of the first metal level. The barrier is usually not needed on the via bottom, and indeed is unwanted because of the contact resistance it introduces between the two metallizations and barrier to copper electromigration across the copper interface of the two metal level. Therefore, the barrier deposition may be tuned to minimize the bottom barrier to the point that its coverage is not continuous or not effective as a barrier. One of the advantages of SIP sputter deposition of the copper seed layer referenced above is that it sputters away the barrier at the bottom of via hole. In this case, in the area of the overhang
46
, the copper directly contacts the underlying dielectric layer
18
. Any copper diffused into the dielectric is likely to be electrically charged and mobile, thus potentially causing a short across the dielectric. Furthermore, in the first level metal overlying the semiconductor devices, the copper may diffuse into the silicon and poison the active semiconductor areas of the transistor.
Accordingly, it is desired especially for copper metallization that the copper be prevented from diffusing into the dielectric layer. This desire is especially urgent for fine geometries in which the via is likely to be unlanded with respect to the underlying copper metallization and in processes in which the barrier layer is absent at the bottom of the via.
SUMMARY OF THE INVENTION
The invention may be summarized as a vertical interconnect structure in integrated circuits and its method of forming. A first metal layer and a first stop layer are formed side by side in a first dielectric layer. A second stop layer is deposited over the first metal layer and the first stop layer, and a second dielectric layer is deposited over the second stop layer. A hole to be used for a vertical interconnect is etched through the second dielectric layer and second stop layer to contact the first metal layer, and metal is filled into the hole. If the hole is offset from the first metal layer, the metal overlies the first stop layer, which acts as a barrier for diffusion of the metal to the first dielectric layer.
The invention is particularly applicable to copper dual damascene in which the first metal layer is filled into and overflows a trench formed in the first dielectric layer and f
Chen Fusen
Dixit Girish A.
Applied Materials Inc.
Goudreau George
Guenzer Charles S.
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