Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-10-17
2003-10-07
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S594000, C257S321000, C257S407000
Reexamination Certificate
active
06630383
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor devices such as non-volatile memory devices and to methods for their fabrication, and more particularly to memory devices which incorporate therein a bi-layer floating gate which comprises an n-type polysilicon layer and a p-type polysilicon layer.
BACKGROUND OF THE INVENTION
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of devices and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
FIG. 1
is cross-section view of a MOSFET transistor
100
having a gate stack. The MOSFET
100
of
FIG. 1
includes therein any suitable semiconductor substrate
102
having therein a source region
104
and a drain region
106
. The gate stack formed on substrate
102
contains a tunnel oxide layer
108
formed from, for example, silicon dioxide, a floating gate
110
formed from polysilicon, an insulating layer
112
formed from a suitable high-K material and a control gate
114
formed from polysilicon. In the MOSFET
100
, the substrate
102
is a p-type substrate, the source
104
and drain
106
are n-type, and the floating gate
110
is an n-type floating gate.
When the MOSFET
100
has a structure as discussed above, the work function between the high-K insulating layer
112
and the floating gate layer
110
can be mismatched depending upon the material utilized to form the high-K insulating layer
112
. Accordingly, in order to minimize the mismatched work function between the floating gate
110
and the high-K insulating layer
112
, the MOSFET
100
must be fabricated with one of a select few high-K materials. This does not permit the formation of the most efficient MOSFET devices. Additionally, a mismatched work function between the floating gate and the high-K insulating layer can hinder the electron transport potential between the floating gate and the tunnel oxide layer.
Hence, there is a need in the art for a structure which overcomes the aforementioned problems and yields an improved gate stack for semiconductor devices.
SUMMARY OF THE INVENTION
In one embodiment, the present invention relates to a method of making a gate stack semiconductor device comprising the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.
In another embodiment, the present invention relates to a method of making a gate stack semiconductor device comprising the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer, wherein the thickness of the p-type polysilicon layer is in the range of about 250 Angstroms to about 550 Angstroms; and forming a high-K insulating layer over the p-type polysilicon layer.
In another embodiment, the present invention relates to a semiconductor device having a gate stack structure, the device comprising: a semiconductor substrate, wherein the semiconductor substrate is a p-type semiconductor substrate; a tunnel oxide layer formed over the semiconductor substrate; a floating gate formed over the tunnel oxide layer; the floating gate comprising: an n-type polysilicon layer formed over the tunnel oxide layer, the n-type polysilicon layer having a nitridated portion opposite the tunnel oxide layer, and a p-type polysilicon layer over the nitridated portion of the n-type polysilicon layer; and a high-K insulating layer formed over the p-type polysilicon layer of the floating gate.
Thus, the present invention overcomes the problems associated with mismatched work functions associated with the gate stacks which contain a high-K insulating layer and an n-type floating gate.
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patent: 5460992 (1995-10-01), Hasegawa
patent: 5567638 (1996-10-01), Lin et al.
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patent: 6281559 (2001-08-01), Yu et al.
patent: 6337246 (2002-01-01), Sobek et al.
patent: 6362045 (2002-03-01), Lin et al.
patent: 6369421 (2002-04-01), Xiang et al.
Cheung Fred T K
Ibok Effiong
Ramsbey Mark T.
Tripsas Nicholas H.
Zheng Wei
Advanced Micro Devices , Inc.
Fourson George
Pham Thanh V
Renner , Otto, Boisselle & Sklar, LLP
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