Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-04-30
2003-04-01
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S736000, C438S739000, C438S947000, C438S952000
Reexamination Certificate
active
06541360
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates generally to integrated circuits and methods of manufacturing integrated circuits. More particularly, the present specification relates to a bi-layer trim etch process used in the formation of integrated circuit gate structures.
BACKGROUND OF THE INVENTION
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to achieving smaller sizes of IC device features is the capability of conventional lithography. Lithography is the process by which a pattern or image is transferred from one medium to another. Conventional IC lithography uses ultra-violet (UV) sensitive photoresist. Ultra-violet light is projected to the photoresist through a reticle or mask to create device patterns on an IC. Conventional IC lithographic processes are limited in their ability to print small features, such as contacts, trenches, polysilicon lines or gate structures.
Generally, conventional lithographic processes (e.g., projection lithography and EUV lithography) do not have sufficient resolution and accuracy to consistently fabricate small features of minimum size. Resolution can be adversely impacted by a number of phenomena including: wavelength of light, diffraction of light, lens aberrations, mechanical stability of the resist, contamination, optical properties of resist material, resist contrast, resist swelling, thermal flow of resist, etc. As such, the critical dimensions of contacts, trenches, gates, and, thus, IC devices, are limited in how small they can be.
Another difficulty arising from the continuing small dimensions involved in the creation of gate structures is the tendency in the lithography process to experience resist erosion and pattern collapse during trim etch processes. During trim etch processes, a significant amount of the resist is normally etched away in a vertical direction, resulting, in a substantial weakening and thinning of the photoresist. This significant reduction of the vertical dimension or thickness of the photoresist from its untrimmed vertical dimension can promote discontinuity thereof, resulting in the photoresist being incapable of providing effective masking in the fabrication of the gate. The resist thickness erosion occurs during etch processes.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need to prevent resist erosion and pattern collapse during trim etch processes. Yet further, there is a need to use imaging layers to define gate structures having small critical dimensions.
SUMMARY OF THE INVENTION
An exemplary embodiment is related to a method of fabricating an integrated circuit (IC). This method can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, using the imaging layer as a hard mask to selectively trim etch the organic underlayer with an isotropic etch in a controlled manner in a high-density plasma etching system to form a pattern smaller than produced by the imaging layer, removing the hard mask imaging layer, and etching the portions of the polysilicon layer using the pattern formed by the organic underlayer.
Another exemplary embodiment is related to a method of forming a gate in an integrated circuit. This method can include providing a gate material layer, providing an organic mask layer over the gate material layer, providing an image layer over the organic mask layer, patterning the image layer, etching the organic mask layer with an undercutting technique, and etching the gate material layer to form gate structures.
Another exemplary embodiment is related to a method of preventing resist erosion and pattern collapse during a trim etch process in the manufacture of a gate structure. This method can include depositing an organic mask material layer over a polysilicon layer, providing a silicon-containing imaging layer that will act as a hard mask for the organic mask material layer, patterning the silicon-containing imaging layer according to a pattern of gate structures, selectively trim etching the imaging layer, etching away portions of the organic mask material layer uncovered by the trimmed imaging layer, and etching the portions of the polysilicon layer uncovered by the organic material layer to form gate structures. The top imaging layer acts as a hard mask to define the patterns in the organic layer, which in turn acts to mask the pattern during subsequent poly etch.
Other principle features and advantages of the invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 5264076 (1993-11-01), Cuthbert et al.
patent: 5346587 (1994-09-01), Doan et al.
patent: 5773199 (1998-06-01), Linliu et al.
patent: 5804088 (1998-09-01), McKee
patent: 5837428 (1998-11-01), Huang et al.
patent: 5858621 (1999-01-01), Yu et al.
patent: 5883011 (1999-03-01), Lin et al.
patent: 6080678 (2000-06-01), Yim
patent: 6096659 (2000-08-01), Gardner et al.
patent: 6136679 (2000-10-01), Yu et al.
patent: 6156629 (2000-12-01), Tao et al.
Bell Scott A.
Lyons Christopher F.
Plat Marina V.
Singh Bhanwar
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Foley & Lardner
Meier Stephen D.
Thomas Toniae M
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