Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2005-07-19
2005-07-19
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S282000, C438S479000, C438S517000, C257S347000, C257S348000
Reexamination Certificate
active
06919236
ABSTRACT:
In one example, a method of forming a transistor above a silicon-on-insulator substrate comprised of a bulk substrate, a buried oxide layer and an active layer, the bulk substrate being doped with a first type of dopant material is disclosed. The method comprises performing a first ion implant process using a dopant material that is of a type opposite the first type of dopant material to form a first well region within the bulk substrate, performing a second ion implant process using a dopant material that is the same type as the first type of dopant material to form a second well region in the bulk substrate within the first well, the transistor being formed in the active layer above the second well, forming a conductive contact to the first well and forming a conductive contact to the second well.
REFERENCES:
patent: 5359219 (1994-10-01), Hwang
patent: 5426062 (1995-06-01), Hwang
patent: 5604707 (1997-02-01), Kuge et al.
patent: 5641980 (1997-06-01), Yamaguchi et al.
patent: 5672995 (1997-09-01), Hirase et al.
patent: 5838047 (1998-11-01), Yamauchi et al.
patent: 5923067 (1999-07-01), Voldman
patent: 5926703 (1999-07-01), Yamaguchi et al.
patent: 6051452 (2000-04-01), Shigyo et al.
patent: 6074899 (2000-06-01), Voldman
patent: 6100567 (2000-08-01), Burr
patent: 6130572 (2000-10-01), Ghilardelli et al.
patent: 6208200 (2001-03-01), Arakawa
patent: 6373321 (2002-04-01), Yamauchi et al.
patent: 6406948 (2002-06-01), Jun et al.
patent: 6468848 (2002-10-01), Awaka et al.
patent: 6486515 (2002-11-01), Jun et al.
patent: 6535052 (2003-03-01), Myono
patent: 6580126 (2003-06-01), Suzumura et al.
patent: 6614699 (2003-09-01), Tanzawa
patent: 6661042 (2003-12-01), Hsu
patent: 6677805 (2004-01-01), Shor et al.
patent: 6693325 (2004-02-01), Ko et al.
patent: 2003/0038670 (2003-02-01), Li
patent: 2003/0207504 (2003-11-01), Fuselier et al.
patent: 0 480 373 (1992-04-01), None
patent: 0 694 977 (1996-01-01), None
patent: 0694977 (1996-05-01), None
Fuselier Mark B.
Wei Andy C.
Wristers Derick J.
Advanced Micro Devices , Inc.
Le Thao X.
Pham Long
Williams Morgan & Amerson P.C.
LandOfFree
Biased, triple-well fully depleted SOI structure, and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Biased, triple-well fully depleted SOI structure, and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Biased, triple-well fully depleted SOI structure, and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3394728