Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-18
2004-08-24
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S207000, C438S349000
Reexamination Certificate
active
06780695
ABSTRACT:
BACKGROUND OF INVENTION
The present invention generally relates to integrated circuits, and more specifically to a method of fabricating a BiCMOS integrated circuit having a raised extrinsic base that utilizes a sacrificial polysilicon layer in the heterojunction bipolar transistor (HBT) device area of the BiCMOS integrated circuit to provide an HBT device area and a complementary metal oxide semiconductor (CMOS) transistor device area which have substantially the same heights during the raised extrinsic base chemical-mechanical polishing (CMP) steps.
BiCMOS integrated circuits combine bipolar transistors, e.g., HBTs, and CMOS transistors on a single chip, providing a variety of functionalities and exploiting the advantages of each type of device. Thus, BiCMOS integrated circuits capitalize on the relatively fast speeds and better analog performance of the bipolar transistors, while exploiting the low power dissipation and high packing density of CMOS transistors.
High-base resistance and high parasitic capacitance between the collector and the base regions in bipolar transistors degrade both the minimum noise and power gain cutoff frequency. In order to reduce the base resistance and parasitic capacitance of bipolar transistors, it is known to form the HBT on a raised extrinsic base; See, for example, co-assigned U.S. application Ser. No. 09/962,732, filed Sep. 25, 2001. The raised extrinsic base in prior art bipolar transistors is formed by utilizing a CMP process. However, when it comes to SiGe BiCMOS structures, there is a topographic issue for CMP since the CMOS gate polysilicon creates a thickness difference, which is similar to the gate height (typically 100-250 nm) between the CMOS device area and the bipolar transistor device area. The height of these two device areas must be adjusted to the same level for the raised extrinsic base CMP.
In one prior art process, se, for example, U.S. Pat. No. 6,492,238 B1, a BiCMOS having a raised extrinsic base region is formed using a reactive-ion etch (RIE) step to etch part of the film on top of the CMOS gate to make the CMOS transistor and bipolar transistor device areas substantially level. Despite being capable of leveling the two device areas, this prior art approach for adjusting the height differential between the HBT and the CMOS transistor device areas is extremely complicated and requires two additional lithographic levels to achieve leveling between the device areas of the CMOS transistor and the HBT.
In view of the drawbacks mentioned with prior art BiCMOS integrated circuit devices having a raised extrinsic base, there is a need for providing a new and improved BiCMOS integration scheme which provides a raised extrinsic base wherein the height of the HBT device area is substantially the same as the height of the CMOS transistor device area. Such an integration scheme should reduce the complexity of the prior art RIE approach as well as reduce the number of lithographic levels that are needed for accomplishing the same.
SUMMARY OF INVENTION
One object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit having a raised extrinsic base.
Another object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit that has reduced base resistance as well as reduced parasitic capacitance.
A further object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which the device area height of the HBT and the CMOS transistor are substantially the same in an interim stage during the raised extrinsic base CMP steps.
A yet further object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which a simple integration scheme is used in forming the same.
A still further object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which fewer lithographic levels than the prior art RIE leveling scheme described above are needed.
An even further object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which the problem associated with narrow spacing between CMOS gates is eliminated.
These and other advantages and objects are achieved in the present invention by forming a BiCMOS integrated circuit having a raised extrinsic base in which a sacrificial polysilicon layer is formed in the HBT device area during the CMOS gate formation. Following CMOS gate formation, a portion of the sacrificial polysilicon layer in the HBT area is removed and thereafter the HBT is formed in the region previously occupied by the removed portion of sacrificial polysilicon. It is noted that after gate formation, but prior to HBT formation, the spaces between each adjacent gate may be filled with a polysilicon placeholder material thereby eliminating the problem associated with narrow spacing between the gates.
Specifically, the present invention provides a method, i.e., a BiCMOS integration scheme, which comprises the steps of:
forming a polysilicon layer atop a surface of a gate dielectric which is located atop a substrate, said substrate having a device area for forming at least one bipolar transistor and a device area for forming at least one complementary metal oxide semiconductor (CMOS) transistor;
patterning said polysilicon layer to provide a sacrificial polysilicon layer over said device area for forming the at least one bipolar transistor, while simultaneously providing at least one gate conductor in said device area for forming at least one CMOS transistor;
forming at least one pair of spacers about each of the at least one gate conductor to provide said at least one CMOS transistor;
selectively removing a portion of said sacrificial polysilicon layer over said device area for forming the at least one bipolar transistor to provide at least one opening; and
forming the at least one bipolar transistor having a raised extrinsic base in the at least one opening.
In an optional embodiment of the present invention, any spaces between the CMOS transistors are filled to prevent problems associated with narrowing of the device spacing during fabrication of the HBT.
REFERENCES:
patent: 5304501 (1994-04-01), Tong
patent: 6117717 (2000-09-01), Carbone et al.
patent: 6667202 (2003-12-01), Suzuki
Ahlgren David C.
Angell David
Chen Huajie
Freeman Gregory G.
Jagannathan Basanth
Abate Joseph P.
Fourson George
International Business Machines - Corporation
Pham Thanh V
Scully Scott Murphy & Presser
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