Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-09-04
2007-09-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S738000, C438S780000
Reexamination Certificate
active
10889416
ABSTRACT:
An improved method of etching very small contact holes through dielectric layers used to separate conducting layers in multilevel integrated circuits formed on semiconductor substrates has been developed. The method uses bi-level ARC coatings in the resist structure and a unique combination of gaseous components in a plasma etching process which is used to dry develop the bi-level resist mask as well as etch through a silicon oxide dielectric layer. The gaseous components comprise a mixture of a fluorine containing gas, such as C4F8, C5F8, C4F6, CHF3or similar species, an inert gas, such as helium or argon, an optional weak oxidant, such as CO or O2or similar species, and a nitrogen source, such as N2, N2O, or NH3or similar species. The patterned masking layer can be used to reliably etch contact holes in silicon oxide layers on semiconductor substrates, where the holes have diameters of about 0.1 micron or less.
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Hsu Ju Wang
Tao Hun Jan
Tsai Ming Huan
Wu Tsang Jiuh
Haynes and Boone LLP
Nguyen Tuan H.
Taiwan Semiconductor Manufacturing Company , Ltd.
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