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Self-aligned silicide (salicide) process for low resistivity...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned silicide process for forming silicide layer...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned silicide process utilizing ion implants for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned silicided MOS devices with an extended S/D junction

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned silicided MOS transistor with a lightly doped drain

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned SOI device with body contact and NiSi2 gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned SOI with different crystal orientation using...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned source pocket for flash memory cells

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned source process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned split-gate NAND flash memory and fabrication...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned split-gate nonvolatile memory structure and a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned stacked gate etch process for fabricating a two-tra

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned STI process using nitride hard mask

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned STI SONOS

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned storage node definition in a DRAM that exceeds the

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned structure and method for confining a melting...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned T-gate carbon nanotube field effect transistor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned transistor and diode topologies in silicon...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Self-aligned transparent metal oxide TFT on flexible substrate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
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Self-aligned trench capacitor capping process for high...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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