Self-aligned silicided MOS devices with an extended S/D junction

Details Self-aligned silicided MOS devices with an extended S/D junction Self-aligned silicided MOS devices with an extended S/D junction

1998-04-20

2000-09-19

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438305, 438530, 438664, 257355, H01L 218238

Patent

active

061210900

ABSTRACT:
A method for fabricating simultaneously a self-aligned silicided and an ESD protective transistor is disclosed. To improve operation speed, the MOS transistor is manufactured with an extended S/D junction; however, there is no salicide and LDD and, with a normal junction in the ESD protective transistor. The method comprises the steps of: thermally grown oxide layers on a defined source/drain region and a poly-Si surface of the gate structure, Then, a photoresist is masked on the functional device, and n-type ions are implanted to form a source/drain region in the ESD protection device. Then the photoresist is removed so as to form a nitride layer on all exposed surfaces of the substrate. An anisotropic etching back the nitride layer to form spacers on sidewalls of the gate structure in the functional device by using a photoresist on the ESD protective device is followed. After that the photoresist on the ESD protection device is removed then a salicidation technology is applied to form the silicide and polycide on S/D and poly-gate, respectively, by using nitride layer as a hard mask. N-type ions are implanted into and/or through the silicide, and thermal annealing is then followed to form an ultra-shallow junction in the functional device. For forming an extended source/drain in the functional device, all nitride layer is removed firstly. Next n-type ions, low energy ion implantation is carried out on the entire substrate. A thick CVD oxide layer is then deposited on all areas. Finally, a RTP anneal is performed to densify the oxide layer and activate dopants to form the extended S/D junction.

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