Self-aligned silicided MOS transistor with a lightly doped drain

Details Self-aligned silicided MOS transistor with a lightly doped drain Self-aligned silicided MOS transistor with a lightly doped drain

1997-12-12

2000-08-08

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438382, 438281, 438275, 438383, H01L 218234, H01L 21336

Patent

active

061001279

ABSTRACT:
A MOS transistor with a self-aligned silicide and a lightly doped drain ballast resistor for ESD protection on a semiconductor substrate is formed with the method in the present invention. The ESD protection devices in a ESD protective region are formed at the same time with the forming of the NMOS, PMOS, or both in a functional region. The transistors with a lightly doped drain (LDD) structure and an ultra-shallow junction can be manufactured. The short channel effect and it's accompanying hot carrier effect is eliminated. ESD damage from external connections to the integrated circuits are kept from the densely packed devices. The self-aligned silicide (salicide) technology employed in the present invention for forming low resistance contacts provides high operation speed with low heat generation. Integrated circuits with ESD hardness and high circuit operation speed of the functional devices are provided by the semiconductor manufacturing process employing the method disclosed.

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P. Fornara et al., Modeling of Local Reduction in TiSi.sub.2 and CoSi.sub.2 Growth Near Spacers in MOS Technologies: Influence of Mechanical Stress and Main Diffusing Species, 1996 IEEE, pp. 73-76.
Ajith Amerasekera, Correlating Drain Junction Scaling Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Perforance of a 0.25 .mu.m CMOS Process, 1996 IEEE, pp. 893-896.

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