Self-aligned transistor and diode topologies in silicon...

Details Self-aligned transistor and diode topologies in silicon... Self-aligned transistor and diode topologies in silicon...

2002-07-12

2004-07-27

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S235000, C438S236000, C438S237000, C438S238000

Reexamination Certificate

active

06767783

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention applies to advanced SiC devices for high-speed, high-power applications such as compact efficient power amplifiers in radar transmitters in airborne and ground-based radar systems and high-power density switching applications such as high-voltage DC-DC converters and inverters.
2. Background of the Technology
Two of the most common types of vertical SiC power transistors are the Static Induction Transistor (SIT) and the Bipolar Junction Transistor (BJT). These devices are described in more detail below.
The SIT is a vertical MESFET or JFET type device wherein the gates are close together resulting in space charge limited current conduction. The device characteristics look much like a triode rather than a conventional FET. The advantages of using an SIT are a result of its high voltage gain and good impedance characteristics, which result in a high power gain. In SiC, the device performance is further enhanced by the high saturation velocity (e.g., 1.5-2× that of Si) and high electric field breakdown strength (e.g., 10× that of Si). Based on SiC's high thermal conductivity and suitability for use at high-temperatures, a silicon carbide SIT device should produce substantial improvements over Si technology.
An SIT can have either PN or Schottky gates. Additionally, current in an SIT is controlled by the electric field applied to the drain and gate regions. Most SIT's in SiC have used Schottky metal gates. See, for example, U.S. Pat. Nos. 5,945,701; 5,903,020; 5,807,773; and 5,612,547. See also Henning et al., “A Novel Self-Aligned Fabrication Process for Microwave Static Induction Transistors in Silicon Carbide,” Electron Device Letters, 21, 578-580 (2000). Using a Schottky gate in an SIT or MESFET will typically limit the junction temperature to about 250° C. because leakage currents exponentially increase through the Schottky gate with increasing temperature.
Much of the early work on the SIT in SiC focused on developing highly uniform, highly controlled epitaxy layers for the drift and channel regions. The early successes of the device were a direct result of improved epitaxy uniformity through the use of wafer rotation and a better understanding of epitaxial growth mechanisms.
Most of the fabrication difficulties currently being experienced in low-cost volume manufacturing can be traced back to the gate-level processing steps. First, the current-carrying capability of the SIT is highly sensitive to the width of the channel regions, which is set by patterned reactive ion etching (RIE). However, after RIE, it is usually necessary to perform thermal oxidation in order to form a high-quality passivation layer over the device. During this step, the oxidation of the sidewall can occur up to five times faster than the planar Si-face of the SiC surface, resulting in variations in the channel width which can be difficult to control precisely. Further, the oxide must be selectively removed from the gate trench bottom and sidewalls, which usually requires wet chemical etching to ensure sidewall oxide removal. This selective removal of oxide along the sidewall is a very challenging step from both an alignment and process point of view.
Once the oxide is removed from the sidewall, the gate Schottky contact can be formed. Due to the very small geometries involved, the gate metal is typically deposited via sputtering, which can induce damage and lower the Schottky barrier, or by angled evaporation. Achieving this coverage, without forming gate-to-source shorts, is extremely difficult as described by Henning, supra.
An additional performance-related problem with the Schottky gate is that the Schottky Barrier metal is deposited on an etched sidewall of SiC. This etched sidewall is not optimal for Schottky deposition, and results in a lowered barrier. Also, the surface is non-planar resulting in a non-planar space charge region in the channel, which can lead to problems with reproducibility or signal fidelity. The non-planar etched sidewall is a result of slight variations in the photolithography pattern. Although it is possible to demonstrate S-band performance with marginal gain, it is clear that an improved process is needed to ensure lower-cost, more reproducible manufacturing of the SiC SIT.
The SiC BJT has been thought to be an attractive device for microwave applications for quite some time. In fact, simulations by R. J. Trew in 1991 indicated that a 6H-SiC BJT with 0.2 &mgr;m thick base doped at 3×10
18
/cm
3
could produce useful power up to 4 GHz in a Class A common-emitter configuration. See Trew et al., “The Potential of Diamond and SiC Electronic Devices for Microwave and Millimeter-Wave Power Applications”, Proc of the IEEE, 79, 598-620(1991). Optimizing the base resistance while maintaining the needed gain is important. Thinning the base decreases the base transit time but increases the base resistance. Adding to this difficulty is that in SiC, the Al acceptor level is nearly 200 meV from the valence band edge and thus not fully ionized at room temperature.
Also, the p-type base contact can be difficult to fabricate in SiC because of the large bandgap. In fact, low-resistivity contacts to p-type SiC have only been formed on heavily doped p-type SiC. The reasons for this can be understood from the thermal equilibrium band diagram of the metal-semiconductor interface (q&PHgr;
M
<q&PHgr;
SiC
). In general, the Schottky barrier (&PHgr;
B
) to majority carrier transport should be reduced as much as possible to provide for an ohmic contact. Since the bandgap and electron affinity (&khgr;) of SiC are fixed, the remaining options for reducing the &PHgr;
B
are to choose a metal with a large work function (&PHgr;
M
) and also to dope the p-type SiC as heavily as possible. P-type ohmic contacts to SiC often use some variation of Al/Ti alloys, and a contact with specific contact resistance of 1.5 &OHgr;·cm
2
on Al-doped samples (NA=2×10
19
/cm
3
) has been reported using an Al/Ti alloy. See Crofton et al., “Contact resistance measurements on p-type 6H-SiC”, Appl. Phys. Lett., 62, 4, 384-386 (1993). The specific contact resistance is a strong function of doping. Although Al melts at approximately 660° C., a 90:10 Al/Ti alloy (by weight) is a mixture of solid and liquid phase at temperatures of 950 to 1150° C., which are typical anneal temperatures used in the formation of ohmic contacts to SiC. See Crofton, supra. See also N. Lundberg et al., “Thermally stable Low Ohmic Contacts to P-type 6H-SiC using Cobalt Silicides”, Solid St. Elect., 39, II, 1559-1565 (1996); and Crofton et al., “Titanium and Aluminum-Titanium Ohmic Contacts to P-Type SiC”, Solid St. Elect. (1997).
More recent experiments using a 90:10 Al/Ti alloy have yielded specific contact resistance ranging from 5×10
−6
to 3×10
−5
on p-type 6H-SiC doped at 1.3×10
19
/cm. On the same material, pure Ti (with a 1 minute, 800° C. anneal) was also used to form ohmic contacts with specific contact resistance ranging from 2-4×10
−5
&OHgr;·cm
2
. Removal of the metals after annealing revealed that the Al-based contact spiked into the SiC, evidenced by pits in the SiC surface up to 2600 Å deep, while the Ti contact exhibited little interfacial reaction. Thus, although Al-based contacts can yield exceptionally low specific contact resistances, the contact can suffer from poor reproducibility and aluminum oxidation during annealing (Al
2
O
3
). See Crofton (1997), supra and Porter et al., “Issues and Status of Ohmic Contacts to P-type Silicon Carbide”, Trans. 3d Int'l. High Temp. Elect. Conf. (HiTEC), Session VII, 3-8 (1996). A more complete summary of these problems can also be found in Casady et al., “Processing of Silicon Carbide for Devices and Circuits,” chapter included in “Processing of Wide Bandgap Semiconductors”, Pearton (ed), William Andrew Publishing and Noyes Publications, 178-249 (2000) (ISBN 0-8151439-5).
One of the most significant improvements possible is th

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