Self-aligned STI process using nitride hard mask

Details Self-aligned STI process using nitride hard mask Self-aligned STI process using nitride hard mask

2001-06-22

2003-04-22

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S353000, C438S405000

Reexamination Certificate

active

06551874

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor integrated circuit (IC) structures, and more particularly to the formation of shallow trench isolation (STI) structures in IC devices.
BACKGROUND OF THE INVENTION
Semiconductor devices are used in a variety of electronic applications, such as personal computers and cellular phones, for example. One such semiconductor product widely used in electronic systems for storing data is a semiconductor memory, and one common type of semiconductor is a dynamic random access memory (DRAM).
A DRAM typically includes millions or billions of individual DRAM cells, with each cell storing one bit of data. A DRAM memory cell typically includes an access field effect transistor (FET) and a storage capacitor. The access FET allows the transfer of data charges to and from the storage capacitor during reading and writing operations. In addition, the data charges on the storage capacitor are periodically refreshed during a refresh operation.
Another memory semiconductor device is called a ferroelectric random access memory (FRAM). An FRAM typically has a similar structure to a DRAM but is comprised of materials such that the storage capacitor does not need to be refreshed continuously as in a DRAM. Common applications for FRAM's include cellular phones and digital cameras, for example.
Memory devices are typically arranged in an array of memory cells. A source/drain region of the cell access FET is coupled to a bitline, and the other source/drain region is coupled to a plate of a respective storage capacitor. The other plate of the capacitor is coupled to a common plate reference voltage. The gate of the transistor is coupled to a wordline. The storing and accessing of information into and from memory cells is achieved by selecting and applying voltages to the wordlines and bitlines.
In fabricating semiconductor devices such as DRAM's, shallow trench isolation (STI) is a technique used to provide electrical isolation between various devices.
FIGS. 1-3
illustrate a prior art STI technique used to isolate active areas of a DRAM array. A crystalline silicon
12
substrate covered with a layer of pad nitride
14
(e.g., 200 nm of silicon nitride) is patterned with trenches
13
, e.g. deep trenches, may have areas of crystalline silicon substrate in regions therebetween. For example, two deep trenches
13
are shown in
FIG. 1
, which may comprise two storage cells or capacitors of a DRAM. A collar
15
is formed within each trench
13
and comprises a thin oxide liner, for example. The trenches
13
are filled with doped polycrystalline silicon (polysilicon)
16
, which is etched back to a depth of, e.g., between 300 to 600 Angstroms below the silicon
12
surface.
Exposed portions of the nitride layer
14
and the polysilicon
16
are covered with a nitride frame
18
. The nitride frame
18
may comprise, for example, 20 nm of silicon nitride. A hard mask
20
comprising boron-doped silicon glass (BSG), or alternatively, tetraethoxysilance (TEOS), is deposited over the nitride frame
18
. BSG is typically used for the hard mask
20
because it is easily reflowable. Generally, for example, about 280 nm of BSG is deposited.
An anti-reflective coating (ARC)
22
comprising, for example, an organic polymer, is deposited over the BSG hard mask
20
, and a resist
24
typically comprising an organic polymer is deposited over the ARC
22
. ARC
22
is typically used to reduce reflection during exposure, which can deteriorate the quality of the image being patterned.
The resist
24
is exposed, patterned and etched to remove exposed portions, in a positive exposure process, although a negative exposure process may be used to pattern the resist
24
.
After an ARC
22
open step, the semiconductor wafer is exposed to an etch process, e.g. an anisotropic etch e.g. in a plasma reactor, to transfer the resist
24
pattern to the BSG hard mask
20
, the nitride frame
18
and nitride layer
14
, as shown in FIG.
2
. Reactive ion etching (RIE) is often used to transfer the pattern to the BSG hard mask
20
, the nitride frame
18
and nitride layer
14
. The etch may stop on the polysilicon
16
and silicon
12
, or alternatively, the etch may include a slight over-etch of silicon
12
to ensure that no portions of the nitride layer
14
remain over the top surface of the silicon
12
. The active areas (AA) are defined as the wafer
10
areas that are protected by the hard mask
20
and therefore are not etched. The resist
24
and the ARC
22
are removed, e.g., in a dry strip using oxygen plasma.
Portions of the wafer
10
not covered by the BSG hard mask
20
are etched to form shallow trenches within the wafer
10
using the BSG hard mask
20
to pattern the trenches, opening the STI area
40
, as shown in FIG.
3
. The polysilicon
16
, collars
15
, and silicon
12
are etched off to a fixed depth, for example, 300 to 350 nanometers, which forms the shallow trench isolation at
40
. The BSG hard mask
20
is then removed prior to any further processing steps. Typically, the trench
40
formed in the silicon
12
and polysilicon
16
will be filled with an insulator such as an oxide, and the wafer
10
is then chemically-mechanically polished (CMP'd) to the nitride layer
14
surface, leaving oxide in the trenches
40
to provide isolation between devices (not shown). The top portion
42
of polysilicon
16
functions as the strap by providing an electrical connection between the deep trench capacitor and the transistor of the memory cell (not shown).
Another prior art STI process is shown in prior art
FIGS. 4-6
. This prior art process is similar to the one shown in
FIGS. 1-3
, with no nitride frame
18
being present. A crystalline silicon
112
substrate covered with a layer of pad nitride
114
is patterned with trenches, e.g. deep trenches, which may have areas of crystalline silicon centered therebetween. A collar
115
is formed within the trenches, comprising a thin oxide liner, for example.
The trenches are filled with polysilicon
116
, which is etched back below the surface of the pad nitride
114
and crystalline silicon
112
. A hard mask
120
comprising BSG or TEOS is deposited over the polysilicon
116
and silicon nitride
114
. An ARC
122
is deposited over the BSG hard mask
120
, and a resist
124
is deposited over the ARC
122
. The resist
124
is exposed, patterned and etched.
After an ARC
122
open step, the semiconductor wafer
100
is exposed to an etch process to transfer the resist
24
pattern to the BSG hard mask
20
, as shown in FIG.
5
. The etch stops on the crystalline silicon
112
in the center region, as shown. The resist
124
and the ARC
122
are removed, and exposed portions of the wafer
100
are etched to form shallow trenches within the wafer
100
using the BSG hard mask
120
to pattern the trenches, as shown in FIG.
3
. The BSG hard mask
120
is then removed prior to any further processing steps.
A problem with using BSG as a hard mask
20
/
120
as in the prior art structures
10
/
100
described herein is misalignment problems between the active areas (AA) and the deep trench region, which can result in defective devices being manufactured. For example, the mask may have been misaligned, which misalignment may be transferred to the wafer
10
/
100
, resulting in an excess amount of polysilicon
16
/
116
being removed (see
FIG. 3
, at
42
) which affects the trench buried strap resistance, and/or an inadequate amount of isolation between active areas. With conventional STI hard mask sequences, the final strap profile is dependent on the initial lithography overlay integrity.
FIG. 7
illustrates a top view of the wafer
100
shown in
FIGS. 4-6
including active areas
112
, STI region
140
and deep trenches
116
. The structure shown in
FIG. 7
shows a properly aligned DRAM having silicon active areas
112
that are adjacent and electrically coupled to strap regions
142
of the deep trench
116
polysilicon. Regions
142
of the DT
116
form

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