Self-aligned silicide process for forming silicide layer...

Details Self-aligned silicide process for forming silicide layer... Self-aligned silicide process for forming silicide layer...

1999-11-12

2001-08-28

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S240000, C438S253000, C438S254000, C438S255000, C438S256000, C438S396000, C438S397000, C438S398000, C438S399000

Reexamination Certificate

active

06281067

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a self-aligned silicide (Salicide) process. More particularly, the present invention relates to a self-aligned silicide process for forming embedded dynamic random access memory (DRAM).
2. Description of the Related Art
In a conventional embedded memory, memory transistors and logic circuit transistors are formed on the same piece of wafer. The advantages of integrating memory and logic transistors together include an increase yield, a shorter cycle time and a lower manufacturing cost. However, due to the different needs of memory transistors and logic transistors, processing steps must be adjusted accordingly. For example, response from logic devices must be as quick as possible. On the other hand, the inter-refreshing time of memory capacitors must be as long as possible. Therefore, the memory transistors must be fabricated in a manner slightly different from the logic devices.
FIG. 1
is a schematic cross-sectional view showing a portion of a conventional embedded DRAM with both logic devices and memory cell transistors therein.
As shown in
FIG. 1
, a substrate
100
that includes a logic device region
102
and a memory cell region
104
is provided. Two transistors
108
and
110
and a capacitor
112
together in the memory cell region
104
constitute a DRAM cell. A transistor
106
is formed in the logic device region
102
.
To increase the speed of operation of the transistor
106
in the logic device region
102
, self-aligned silicide layers
114
are formed over the transistor terminal regions. However, in order to extend the inter-refreshing period of memory cell, resistance at the junction between the capacitor
112
and the source/drain region
116
of the transistor
110
must be increased. Consequently, a silicide layer is usually not formed over the source/drain regions of the transistors
108
and
110
in the memory cell region
104
.
In general, before self-aligned silicide layers are formed over the terminal regions of the transistor
106
, a blocking layer is formed over the transistors
108
and
110
. The blocking layer is removed after the self-aligned silicide process is complete.
Since no silicide layer covers the source/drain regions
116
of the transistors
108
and
110
, resistance at source/drain junctions is high. However, due to the absence of a silicide layer, resistance at the word line or gate junctions of the transistors
108
and
110
will also be high. Hence, operating speed of the memory cell will drop.
Ideally, silicide layers are formed over the gate terminals and the source/drain terminals of transistors in the logic device region as well as the gate word lines of transistors in the memory cell region. No silicide layer is formed over the source/drain regions of the transistors in the memory cell region. However, such a configuration can hardly be achieved through a conventional process.
SUMMARY OF THE INVENTION
The invention provides a self-aligned process for forming a silicide layer. A substrate that includes a memory cell region and a logic circuit region is provided. A first transistor and a second transistor are formed over the substrate. The first transistor is formed in the logic circuit region and includes a first gate conductive layer and a first source/drain region. The second transistor is formed in the memory cell region and includes a second gate conductive layer and a second source/drain region. A blocking layer is formed over both the first transistor and the second transistor. A portion of the blocking layer is removed to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer. The remaining blocking layer still covers the second source/drain region. A metal silicide layer is formed over the first gate conductive layer, the first source/drain region and the second gate conductive layer.
According to one embodiment of this invention, the steps of removing a portion of the blocking layer include forming a patterned photoresist layer over the second source/drain region. The blocking layer is etched to expose the first gate conductive layer, the first source/drain region and the second gate conductive layer while using the patterned photoresist layer as an etching mask. The patterned photoresist layer is removed.
According to one embodiment of this invention, the steps of forming the patterned photoresist layer include depositing photoresist material over the blocking layer to form a photoresist layer. The photoresist layer is next patterned to remove the portion of photoresist layer in the logic circuit region. The remaining photoresist layer is etched back to expose the blocking layer above the second gate conductive layer. The residual photoresist layer becomes the patterned photoresist layer above the second source/drain region in the aforementioned description.
According to another embodiment of this invention, the patterned photoresist layer can be formed by depositing photoresist material over the blocking layer to form a photoresist layer. The photoresist layer is next exposed to light through a special photomask. Transparency of the photomask in region that corresponds to the memory cell region is only about 20% to 80% of the transparency of the photomask in region that corresponds to the logic circuit region. The light-exposed photoresist layer is developed to form the patterned photoresist layer.
Accordingly, the present invention is to provide a self-aligned silicide process capable of forming silicide layers over the gate word lines in DRAM and silicide layers over the transistors in a logic circuit region. In other words, silicide layers are formed over the transistor terminals in the logic device region as well as over the gate word lines of transistors in the memory cell region. However, no silicide layer is formed over the source/drain regions of the transistors in the memory cell region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5866451 (1999-02-01), Yoo et al.
patent: 5998252 (1999-12-01), Huang
patent: 6004843 (1999-12-01), Huang
patent: 6015730 (2000-01-01), Wang et al.
patent: 6069037 (2000-05-01), Liao
patent: 6074908 (2000-06-01), Huang
patent: 6133130 (2000-10-01), Lin et al.
patent: 6174758 (2001-01-01), Nachumovsky
patent: 6177306 (2001-01-01), Wu

Affiliated with

Also associated with

Rating

Self-aligned silicide process for forming silicide layer... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self-aligned silicide process for forming silicide layer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned silicide process for forming silicide layer... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2522063