Forming retrograde channel profile and shallow LLDD/S-D...

Forming self-align source line for memory array

Forming silicon trench isolation (STI) in semiconductor...

Forming strained source drain junction field effect transistors

Forming trench isolators in semiconductor devices

Forming ultra-shallow junctions

Formulation of high performance transistors using gate trim etch

Formulation of multiple gate oxides thicknesses without...

Four-bit finfet NVRAM memory device

Four-transistor Schmitt trigger inverter

Four-transistor static-random-access-memory and forming method

Fringing capacitor structure

Fringing capacitor structure

Front stage process of a fully depleted silicon-on-insulator...

Full silicide gate for CMOS

Fully amorphized source/drain for leaky junctions

Fully depleted silicon-on-insulator CMOS logic

Fully depleted SOI MOSFET arrangement with sunken...

Fully depleted SOI transistor with elevated source and drain

Fully depleted strained semiconductor on insulator...