Full silicide gate for CMOS

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257S369000, C257SE21632, C257SE21636, C257SE21637

Reexamination Certificate

active

07955921

ABSTRACT:
A method is provided for fabricating an n-type field effect transistor (“NFET”) and a p-type field effect transistor (“PFET”) in which the NFET and PFET are formed after which a protective hard mask layer, e.g., a dielectric stressor layer is formed to overlie edges of gates, source regions and drain regions of the PFET and NFET. Sputter etching can be used to remove a portion of the protective hard mask layer to expose the gates of the PFET and NFET. The semiconductor elements can be etched selectively with respect to the protective hard mask layer to reduce a thickness of the semiconductor elements. A metal may then be deposited and caused to react with the reduced thickness semiconductor element to form silicide elements of the gates.

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A. Veloso et al., “Dual Work Function Phase Controlled Ni-FUSI CMOS (NiSi NMOS, Ni2Si or Ni31Si12 PMOS): Manufacturability, Reliability & Process Window Improvement by Sacrificial SiGe Cap,” 2006Symposium on VLSI Technology Digest of Technical Papers, IEEE 2006.

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