Formulation of high performance transistors using gate trim etch

Details Formulation of high performance transistors using gate trim etch Formulation of high performance transistors using gate trim etch

1998-04-29

2000-08-29

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438300, 438301, 438302, 438303, 438305, 438306, 438307, 438229, 438230, H01L 21336

Patent

active

061107859

ABSTRACT:
The present invention is directed to a new and improved technique for formation of metal oxide semiconductor field effect transistors. In particular, the method involves formation of an initial gate structure that is wider than the desired final channel length of the completed transistor. Thereafter, an initial heavy-doping step is applied to the drain and source regions of the device. The width of the gate structure is then patterned and etched back to the desired final channel length of the device. A second, light-doping LDD implant is performed to complete the source and drain regions of the finished device.

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patent: 5032535 (1991-07-01), Kamijo et al.
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patent: 5424234 (1995-06-01), Kwon
patent: 5565369 (1996-10-01), Ko
patent: 5869378 (1996-04-01), Michael

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