Forming strained source drain junction field effect transistors

Details Forming strained source drain junction field effect transistors Forming strained source drain junction field effect transistors

2002-06-20

2003-10-28

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S301000, C438S303000, C438S305000

Reexamination Certificate

active

06638802

ABSTRACT:

BACKGROUND
This invention relates generally to integrated circuits and, particularly, to techniques for making metal oxide semiconductor field effect transistors (MOSFETs).
Progressively, integrated circuits are being made to smaller and smaller dimensions. Producing smaller dimensions generally means forming junctions for integrated circuit transistors that are shallower. These shallower junctions may have relatively low resistivity to maintain the current drive of the resulting transistors. Generally, producing lower resistance junctions involves increasing junction doping concentration. However, producing shallower junctions while increasing doping concentration may be difficult because of the limits imposed by dopant solid solubility in silicon.
In other words, it is desirable to make shallow, heavily doped junctions, but these two goals may be inconsistent with one another. In the past, junctions have been scaled using reduced energy ion implants and increased thermal ramp speeds in rapid thermal processing hardware. Increasing the ramp speed of the rapid thermal processing thermal anneal process allows a higher peak temperature that may improve solid solubility. The increase in solid solubility allows the incorporation of more dopants and, hence, lower sheet resistance for the same junction depth. Similarly, the faster anneal times reduce the amount of dopant diffusion.
The ion implant energy of the source/drain implant and source/drain extensions also contributes to a shallower junction. An ion implant can produce shallow, very high concentrations of dopants, but conventional rapid thermal processing technology cannot activate anymore dopant. The concentration of the source/drain extensions has reached the solid solubility limit of conventional rapid thermal processing.
Thus, there is a need for still shallower junctions while maintaining adequate resistivity.


REFERENCES:
patent: 5266510 (1993-11-01), Lee
patent: 5566212 (1996-10-01), Boytim et al.
patent: 6319798 (2001-11-01), Yu
patent: 6368947 (2002-04-01), Yu
patent: 6475885 (2002-11-01), Sultan
patent: 6486510 (2002-11-01), Brown et al.
patent: 2002/0086502 (2002-07-01), Liu et al.

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