Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-02-11
2002-05-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S144000
Reexamination Certificate
active
06395587
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to semiconductor devices having a silicon-on-insulator structure that dissipates charge within the floating body of the device.
2. Background Description
Semiconductor devices with a silicon-on-insulator (SOI) structure have an insulator layer buried under a thinner silicon layer that typically contains the source and drain regions of one or more field-effect transistors. SOI devices, more specifically, may be categorized as having one of two basic structures. The first structure includes a thin layer of silicon, usually 0.5 &mgr;m or less, on top of a thick insulator layer, which serves as the entire substrate for the device. Silicon-on-sapphire devices exemplify this type of SOI. The second structure includes an insulator layer sandwiched between a silicon substrate and an overlying silicon layer. Separation by implanted oxygen (SIMOX) devices and those made by wafer bonding exemplify this type.
SOI semiconductor devices have attributes that make them suitable for a variety of applications. For example, SOI devices are more radiation resistant and less subject to alpha-particle upsets than their bulk silicon counterparts, mainly because their ability to apply a negative bias at their back interfaces. As a result, SOI devices are often employed in space and defense electronics. SOI devices also have reduced parasitic drain capacitance realized through their use of a thick insulator. This allows the device to attain speeds faster than those formed on bulk silicon. An additional advantage is that complementary metal-oxide silicon (CMOS) devices having an SOI structure do not suffer from latch-up problems and thus are able to achieve higher packing densities than non-SOI structures. Other advantages include improved isolation properties, higher noise margins, and relatively low-standby power.
For all their advantages, conventional SOI devices have significant drawbacks which prevent them from performing optimally. For example, in conventional SOI structures, the buried oxide (insulator) layer beneath the silicon dielectrically isolates the device from the base, i.e., the underlying silicon substrate. As a result, charge often develops within the floating body of the device which does not have the capability to dissipate.
U.S. Pat. No. 5,264,721 discloses one approach for solving this problem. As shown in
FIG. 1
, this structure includes an insulator layer
2
of SiO
2
formed on a silicon substrate
1
. Atop the insulator layer is a p-type silicon layer
3
, followed by an isolation layer
4
and a gate electrode
5
. In order to suppress a kink phenomenon in the device, aluminum ions are implanted into a source region
6
′ of the silicon layer to a depth which reaches a p-n junction between silicon layer
3
and the source region, which is separated from a drain region
7
by a channel
31
. The implanted aluminum ions cause a leakage current to form across the source p-n junction which eliminates any potential difference that may exist between the source region
6
′ and the portion of the silicon layer
31
′ located beneath the channel
31
. This prevents silicon layer
31
′ from floating and suppresses the kink phenomenon.
The above approach is undesirable for a number of reasons. First, it may require use of a separate masking level. Second, it implants a non-traditional species (Al) that may adversely affect operation of the resulting device.
Other approaches have been developed to dissipate the body charge in an SOI structure. These approaches involve intentionally creating junction defects in the SOI structure that result in charge leakage into the base. These conventional methods result in the formation of a source/drain with some “leakiness.” However, during subsequent processing (e.g., annealing), the source/drain regions re-crystallize, which reduces the “leakiness” of the junction.
A need therefore exists for a method of forming a semiconductor device with an SOI structure that produces permanently formed junction leakage paths that consistently and efficiently dissipate charge formed in the body of such a device.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method for forming a semiconductor device having an SOI structure which operates with improved performance compared with conventional SOI devices.
It is another objective of the present invention to achieve the aforementioned objective by forming junction leakage paths in the source and drain regions of the SOI structure that will consistently and efficiently dissipate body charge during operation of the device.
It is another objective of the present invention to form the aforementioned permanent junction leakage paths by implanting the source and drain regions of the SOI device with amorphizing species, thereby enabling the source and drain junctions to retain their leakage characteristics in spite of any subsequent processing steps that may be required to produce the finalized SOI product.
It is another objective of the present invention to provide a method of the aforementioned type that reduces body charge, may not require use of separate masks, uses traditional species (e.g., Ge, Si) to produce a uniform pre-amorphized layer, and causes leakage by creating extended crystalline defects.
It is another objective of the present invention to provide a semiconductor device having an SOI structure with increased resistance to floating-body effects.
These and other objectives of the present invention are achieved by providing a method in which source and drain regions of an SOI structure are implanted with an amorphizing species (e.g., germanium or silicon) to a predetermined depth. The implant depth and concentration is selected so that the source and drain are fully amorphizing (i.e., the amorphous species is implanted throughout the entire thickness of the source and drain) to ensure that p-n leakage junctions are formed that dissipate body charge throughout the life of the device. As a result, the SOI structure of the claimed invention is fabricated with greater simplicity while using otherwise traditional fabrication techniques.
Another advantage is that the junction leakage produced by the claimed invention reduces the so-called “kink effect.” In a floating body SOI device, charge tends to build up in the body. This causes the threshold voltage to decrease and consequently the drain current to increase. This increase in current is observed as a “kink” in the transistor output characteristics. By producing leakage in the body, the present invention suppresses this kink effect, thereby improving operational performance.
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Crowder Scott
Schepis Dominic J.
Sherony Melanie J.
Anderson Jay H.
Berry Renee R.
International Business Machines - Corporation
Nelms David
Whitman, Curtis & Christofferson P.C.
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