Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-11-01
2010-10-12
Blum, David S (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21409, C257SE29226
Reexamination Certificate
active
07811887
ABSTRACT:
Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices.
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Givant Amichai
Irani Rustom
Blum David S
Eitan Mehulal Law Group
Saifun Semiconductors Ltd.
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