Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-06-27
2001-02-27
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S528000, C438S566000
Reexamination Certificate
active
06194259
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. The invention relates more specifically to the manufacture of submicron, high-performance semiconductor devices using nitrogen implants to obtain a retrograde channel profile in an NMOS device and to obtain shallow LDD regions in a PMOS device.
2. Discussion of the Related Art
The semiconductor industry is increasingly characterized by a growing trend toward fabricating larger and more complex circuits on a given semiconductor chip. This is being achieved by reducing the size of individual devices within the circuits and spacing the devices closer together. The reduction of the size of individual devices and the closer spacing brings about improved electrical performance.
There is increasing interest in MOS integrated circuits in which the component devices have gate dimensions as small as 0.35 &mgr;pm or less. Devices having such small dimensions suffer from certain problems that are not of serious concern when the gate dimensions are greater than about 1 &mgr;m.
The threshold voltage, V
T
, is one of the most important parameters of a MOSFET and is defined as the gate voltage at the onset of strong inversion. In many MOS integrated circuit applications it is critical to be able to establish and maintain a uniform and stable threshold voltage, V
T
. There are several factors that affect the value of the threshold voltage, however, the most feasible factor to manipulate in order to adjust the threshold voltage was the amount of substrate doping, N
A
, in n-channel devices, and N
D
in p-channel devices. However, merely increasing the substrate doping causes adverse effects in other MOSFET characteristics, such as lower junction-breakdown voltages, larger junction capacitances, and lower carrier mobilities. The latter two adversely affect the speed of the device. As can be appreciated, the adjustment of threshold voltages was a delicate balancing act between obtaining a usable and stable threshold voltage and the adverse effects caused by the increase in substrate doping. The development of ion implantation for adjustment of threshold voltage provided a method for the reliable production of MOS integrated circuits. The ion implantation made it possible to select the substrate-doping value without having to consider its impact on threshold voltage value because ion implantation can be used either to increase or decrease, by compensation, the net dopant concentration at the silicon surface. Because of this, substrate doping can theoretically be selected strictly on the basis of optimum device performance since threshold voltage can be adjusted by an implant process. The threshold voltage adjust implant technique involves implantation of boron, phosphorus, or arsenic ions into the surface of the substrate of a MOSFET. The threshold voltage adjust implant is done at an energy selected to place the peak of the implant slightly below the silicon substrate surface. By implanting ions near the Si surface, a nonuniformly doped channel is produced. Besides shifting the threshold voltage the ion implant alters the MOSFET behavior in several ways compared to devices having uniformly doped channels. The threshold voltage adjust implant introduces extra ions into the channel depletion region, causing its width to be modified. In addition, the non-uniform doping profile changes the long-channel subthreshold characteristic such as the slope of the log I
D
vs. V
GS
curves, and the punchthrough behavior of short-channel devices.
However, as the device dimensions have continued to decrease below 0.35 &mgr;m, short-channel effects become very important. In order to improve short-channel effects, channel engineering as well as shallow LDD junctions are required. For example, it is known that a retrograde channel profile improves short-channel behavior. As known in the art, a retrograde channel profile is one in which the peak concentration is below the surface. It has been found that boron implants, because of the high diffusivity of boron ions, have not been satisfactory. Although the boron ions can be implanted with an initial precise and predictable concentration profile, subsequent high temperature processes cause the boron ions to diffuse to a great extent into the substrate resulting in a substantially uniform concentration profile in the substrate. Because the desired concentration profile in an NMOS device is a retrograde concentration profile, the continued use of boron has been problematic. One attempt to alleviate this problem has been to use indium rather than boron as a doping agent. In a PMOS device, it is desired that the LDD (lightly doped drain) regions be very shallow to avoid punchthrough and other problems. Therefore, the boron implant must be very shallow and the shallowness of the boron implant must be maintained throughout the subsequent processes. However, as in the case of the retrograde concentration channel profile, the high diffusivity of boron prevents the maintenance of the shallow boron implant.
Therefore, what is needed is a method to control the profile of the boron implant to achieve and maintain a retrograde channel concentration profile in an NMOS device and a method to control the profile of the boron implant in a PMOS device to obtain and maintain shallow LDD regions.
SUMMARY OF THE INVENTION
The present invention is directed to a method of forming a retrograde channel concentration profile in the NMOS region of a semiconductor device. The retrograde channel concentration profile is formed by implanting nitrogen ions into the NMOS region at a selected concentration and energy and by implanting boron ions into the NMOS region at a selected concentration and energy. The nitrogen ions are implanted at a selected concentration in the range of 1×10
13
to 2×10
15
ions per cm
2
and at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted at a selected concentration in the range of 1×10
12
to 1×10
14
ions per cm
2
and at a selected implantation energy in the range of 5-50 KeV.
The present invention is further directed to a method of forming shallow LDD regions in a PMOS region of a semiconductor device. The shallow LDD regions are formed by implanting nitrogen ions into the source and drain regions at a selected concentration and energy implant level and by implanting boron ions into the source and drain regions at a selected concentration. The nitrogen ions are implanted into the source and drain regions at a selected concentration in the range of 1×10
13
to 2×10
15
ions per cm
2
and at a selected implantation energy in the range of 5-50 KeV. The boron ions are implanted into the source and drain regions at a selected concentration in the range of 1×10
14
to 5×10
15
ions per cm
2
and at a selected implantation energy in the range of 10-20 KeV.
The present invention is still further directed to a method of forming a retrograde channel concentration profile in the NMOS region of a cmos semiconductor device and to a method of forming shallow LDD regions in the PMOS region of the cmos semiconductor device. The retrograde channel concentration profile is formed by masking the PMOS region and implanting nitrogen and boron ions into the NMOS region at selected concentrations and energy levels. The nitrogen ions are implanted into the NMOS region at a selected concentration in the range of 1×10
13
to 2×10
15
ions per cm
2
an at a selected implantation energy in the range of 10-100 KeV. The boron ions are implanted into the NMOS region at a selected concentration in the range of 1×10
12
to 1×10
14
ions per cm
2
and at a selected implantation energy in the range of 5-50 KeV. The mask is removed from the PMOS region, the NMOS region is masked and the shallow p-n junction is formed by implanting nitrogen and boron ions into the PMOS region at selected concentrations and energy levels. The nitrogen ions are im
Hao Ming-yin
Nayak Deepak K.
Advanced Micro Devices , Inc.
Blum David S
Bowers Charles
Nelson H. Donald
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